Customer Reviews

Step-by-step Functional Verification with SystemVerilog and OVM

5 star:		(8)
4 star:		(6)
3 star:		(0)
2 star:		(1)
1 star:		(0)

 

 

The book lays out the verification methodology very well. The problem is that the book was based on OVM 1.0.1. OVM 2.1.1 was the version in use when I bought this book. With this version a lot of the examples in this book are out of date and useless. A good example is chapter 8 which covers sequences it talks about virtual sequencers these have been deprecated, some of the sequence port are gone also. This makes the majority of chapter 8 and later chapters and examples which use virtual sequencer useless. In short the book is too expensive to buy for the information it has in it now. Find a book that has been written more recently.

Reviewer: José Calero Title: CTO Company: DS2

Book: Step-by-Step Verification Using SystemVerilog and OVM

Finally, a nice to read and straight-forward book that clarifies the basic and advanced concepts behind modern SoC verification and behind the OVM methodology.

Before reading this book, I had the feeling that OVM, although very
powerful, had a painful and long learning curve. This is not anymore the case. The book drives you from the verification basics to the advanced topics, and it does that for both the newcomer and the verification expert willing to know about OVM. In particular, for readers with a previous experience in SoC design, the author introduces the "module-based" approach to verification environments which helps to change-the-mind towards a full class-based verification system.

The book is full with a selected set of example the author uses to describe the topics in a constructive manner (piece of code presented first are used later within examples that describe more complex concepts or complete scenarios). Part 5 of the book, "Environment Implementation and Scenario Generation", wraps-up all the concepts with a complete example.

The book is extremely good for any verification engineer. I think it can be very good also for R&D managers to understand better the verification process and flow, in the first chapter the book makes it very clear and well organized.
For junior and senior verificaion engineers the book is very usefull, first to improve and learn verification skills and methodologies, secondly, it explains the system verilog main egines very clear and short with very good examples.
For OVM the book is wonderfull. Since OVM does not have a real specification with examples, this book is the best I found to understand and use OVM in the best and fastest way.
Bottom line, I think it is the best book for OVM that I could find, as well as for engineers that do not have SW programming background in Object Oriented language it explains it very well and clear.
I'm using OVM in my day by day job as a senior verification engneer and this book helped me out in several topics that were not clear for me.
I strongly recomend this book!
Claudiu

I needed to become deeply familiar with OVM. This book is an excellent source of information that I have not found anywhere else. Iman is thorough and detailed. THe Step-by-Step layout works great.

But just note that the OVM examples in the 2nd half of the book are based on OVM-1.01. The OVM-1.01 examples in the book do not compile without some editing if you are using the latest release of OVM (I am currently using ovm-2.0.1). I emailed the author about this. [...]

The good news is editing the examples is not that bad if you grep through the ovm-2.0.1/src directory for information. The examples are well-put together and highlight Iman's concepts well. And once the edits are made, the examples run great.

(disclaimer - we're being offered an extra copy for a review)

Even though though the extra copy is an incentive to write this review, the offer did not in any way suggest using any bias. I've been a verification engineer for the better part of 20 years and I hope you will consider this review impartial.

So far I have carefully read up through part 3 (chapters 1-9, pages 1-235 of 520)

Overall, this is a very concise and well thought out reference for anyone wishing to become proficient at writing SystemVerilog/OVM testbenches. While prior knowledge of other verification methodologies and languages are not required to understand the concepts and structure of testbenches using OVM laid out in this book, it is required if you actually want to create verification testbenches and tests using OVM. This book does not provide that background.

Part 1 - Chapters 1, 2 & 3

These chapters are dedicated to outlining verification and verification methodology principles. It is a must read if you've never been exposed to a well thought out verification methodology. Of the hundreds of verification candidates I've interviewed, only around 10% appear to know this. If all you get out of this are the principles here, this book will be worth your money.

Part 2 - Chapters 4 & 5

These chapters review some new things that are in SystemVerilog. Although it suggests that they are "All About SystemVerilog" they are not. This is good as I expected and wanted this book to be more about verification and OVM than SystemVerilog. Don't look to this book as a SystemVerilog reference. It is interesting that there is a separate chapter for "SystemVerilog as a Verification Language". While the brief list of differences are true, both designers and verification would benefit from the explanations.

Part 3 - Chapters 6, 7, 8 & 9

This is the meat of the book (so far). Individual pieces of the OVM method are illustrated with examples and text. The author does an admirable job of concisely providing and describing code that, while dry, is fairly clear. It tends to be somewhat minimalistic showing only form and structure. I would prefer a little more reasoning behind why certain things were done in certain ways - not just for verification but why was the methodology constructed the way it was.

That's all I've gotten to and will refrain from comment on what I have not read yet. Hopefully I will be able to add more commentary when I am finished with the book.

In summary, this is an excellent choice (and one of the few!) for verification engineers who need to come up to speed with OVM. On the plus side, the material encourages what I would consider the best verification practices available today. On the minus side, the text and examples are sometimes a little to brief and when I try to use it as a reference, it is sometimes hard to find what I need quickly.

I believe that even a college graduate could benefit from this book, as it shapes one's thinking toward a future where design verification is more
important than design. As a design and verification engineer, I realize
that books like this one are essential for my continued education. I have used almost every verification tool you can think of. I have learned these tools with and without help. Trust me, this book is the kind of help you need.

A great deal of the time, thought and effort must have been put into the teaching of SystemVerilog in this book, because I was able to pick up the concepts with ease. I saw original examples and great detailed explanations of the features of SystemVerilog. This book also provided me with an in depth look at what OVM is and how it helps to simplify the complex task of verifying ASICs. Without OVM we are limited to verifying the simple and small FPGAs in this world. Without learning SystemVerilog we would relegated to doing VHDL for the rest of our short careers. This book teaches both OVM and System Verilog. Read this book and you will understand why you need these tools and how you can benefit from this new technology.

I purchased this book for a customer's 3-person verification team to use as a reference for learning System Verilog, and to get an overview of OVM. Of all the books they had, this one was their favorite, and they all commented on how well it was organized, and found examples on most subjects they looked up.

This is a great book for Verification Engineers. It helps you think from a verification side, moreover it gives you the tools to do it. The coverage of Language is great

This book has been an essential resource for our team in moving our verification methodology to OVM. The opening chapters provide a detailed introduction to verification for the inexperienced, while those of us with experience in other methodologies have found the book to be an excellent reference in both SystemVerilog and OVM. The combination of this book and the OVM manuals has been vital to our OVC development (it is based on 1.0.1, but still applicable to 2.0.1).

A minor negative point is that the book doesn't really highlight the OVC concept. (We found it useful to follow the guidelines in the OVM User Manual for the initial stages of basic OVC development). Plus the index is not very detailed - it's harder than it should be to find what you're looking for.

However, the negatives should not put you off obtaining this book if you use OVM - it is an essential supplement to the manuals.

The book is well written and describes both System Verilog and OVM. It is the first book to combine these two and my experience shows that this technology is being adopted by many companies, making this book a necessary item in your book shelf. The author has taken great care to go into a lot of details and the book needs to be read cover-to-cover. Unfortunatley, for traditional design & verification engineers, the object-oriented paradigmn is a hard concept to master and where this book lacks is in examples. The x-bar example developed by the author and described in the book is also available elsewhere. It is my suggestion that the author add several more examples from different domains starting from the very simple to the complex. These examples should be downloadable too. Description and use of the "factory concept" should also be enhanced.

In summary this book will reduce the time required to master the OVM methodology and is a "must buy". I have recommended that my entire team use this book to migrate to the OVM methodology as quickly as possible.