Previous books on this subject have concentrated just on the VHDL hardware description language without really teaching the design process. This new reference really shows how to design with VHDL in a synthesis context.
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Most Helpful Customer Reviews
4 of 4 people found the following review helpful:
1.0 out of 5 stars
poorly organized book,
By A Customer
This review is from: Structured Logic Design with VHDL (Hardcover)
This was the required text, for a very limited time of course, for my vhdl course. The book is horrible. It is poorly organized, with very few examples, and contains paragraph after paragraph of verbage. Everyone I knew at that class relied primary on other texts. This book seems to be intended for "advanced" vhdl users, since they're the only ones who could possibly understand the writing and the hardware devices that are modeled in the examples. then again, if you're a real pro, would you have the time and patience to read this book given its inferior quality.
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