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System-on-a-Chip: Design and Test
 
 
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System-on-a-Chip: Design and Test [Hardcover]

Rochit Rajsuman (Author)
1.0 out of 5 stars  See all reviews (1 customer review)

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Book Description

1580531075 978-1580531078 June 2000
Starting with a basic overview of system-on-a-chip (SoC), including definitions of related terms, this book helps you understand SoC design challenges, and the latest design and test methodologies. Part One features a discussion of SoC -related design difficulties including hardware-software co-design, reuse design, and cores design. It concludes with the information you need to develop test benches at both the cores and SoC level. Part Two contains a review of the challenges you face in testing SoC and test methodologies for overcoming these hurdles. You also get an overview of material handling, speed-binning, and production flow to apply your knowledge to actual production processes.

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About the Author

Rochit Rajsuman manages test research at Advantest America R & D Center in Santa Clara, California. He received his B.Tech. in Electrical Engineering from K.N. Institute of Technology, India, his M.S. in Electrical Engineering from the University of Oklahoma, and his Ph.D. in Electrical Engineering from Colorado State University. He is a senior member of the IEEE and a Golden Core member of the Computer Society.

Product Details

  • Hardcover: 294 pages
  • Publisher: Artech House (June 2000)
  • Language: English
  • ISBN-10: 1580531075
  • ISBN-13: 978-1580531078
  • Product Dimensions: 9.4 x 6.4 x 1 inches
  • Shipping Weight: 1.5 pounds (View shipping rates and policies)
  • Average Customer Review: 1.0 out of 5 stars  See all reviews (1 customer review)
  • Amazon Best Sellers Rank: #2,321,140 in Books (See Top 100 in Books)

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22 of 23 people found the following review helpful:
1.0 out of 5 stars Needs Major work, January 29, 2001
By A Customer
This review is from: System-on-a-Chip: Design and Test (Hardcover)
I've worked on SoC's and do not consider myself an expert but this book is not worth the money. From the title you would expect this book to be about design and test of SoC's. The author does not present any new or insightful design techniques or testing strategys that a person who has designed an ASIC before does not know. He covers basic rules in very general terms with out real specific details. The books seem to be just an ad-hoc hodge podge of every day asic guidelines that are summerized in 200+ pages. Even if you have never designed an ASIC before this book would not help you it is way to general and very vague. I would invest in talking to an ASIC designer in one's company. This books is not worth the money even for the new ASIC designer.
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Inside This Book (learn more)
First Sentence:
In the mid-1990s, ASIC technology evolved from a chip-set philosophy to an embedded-cores-based system-on-a-chip (SoC) concept. Read the first page
Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
large embedded memories, input for this option, dual insertion, bus functional model, test access mechanism, chip integrator, logic tester, synthesis script, tester channels, silicon prototype, memory compilers, memory tester, coupling faults, bidirectional pin, core provider, test reuse, microprocessor core, test synthesis, wafer sort, dedicated pin, scan chains, bridging faults, static timing analysis, boundary scan, dummy cells
Key Phrases - Capitalized Phrases (CAPs): (learn more)
Test Conf, Mentor Graphics, Power Down, Kluwer Academic Publishers, Solid State Circuits, Englewood Cliffs, New York, Prentice Hall, Cadence Design Systems, Test Symp, Avanti Corporation, Design Center, Infinite Technology, Texas Instruments
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