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SystemVerilog for Design Second Edition Kindle Edition

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Length: 418 pages

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Editorial Reviews

From the Back Cover

SystemVerilog is a rich set of extensions to the Verilog Hardware Description Language (Verilog HDL). SystemVerilog for Design describes the correct usage of these extensions for modeling digital designs. These important extensions enable the representation of complex digital logic in concise, accurate, and reusable hardware models. All key SystemVerilog design features are presented, such as declaration spaces, two-state data types, enumerated types, user-defined types, structures, unions, interfaces, and RTL coding extensions. Emphasis is placed on the proper usage of these enhancements for simulation and synthesis. Design engineers, engineering managers and engineering students working with all sizes and types of digital designs, whether FPGA, ASIC or full custom, will find this book to be an invaluable learning tool and reference guide.

The second edition of this book reflects the official IEEE 1800-2005 SystemVerilog standard. This IEEE SystemVerilog standard adds new capabilities, clarifications, and changes to the Accellera 3.1 SystemVerilog upon which the first edition of this book was based.

Significant updates and revisions in the new edition include:

A new chapter showing how to use SystemVerilog packages with single-file and multi-file compilers.

-  New code examples illustrating correct usage of the IEEE version of SystemVerilog.

-  Updated coding guidelines reflecting the capabilities of current simulator and synthesis Electronic Design Automation tools such as digital simulators and synthesis compilers.

"SystemVerilog makes it easier to produce more efficient and concise descriptions of complex hardware designs. The authors of this book have been involved with the development of the language from the beginning, and who is better to learn from than those involved from day one?"

— Greg Spirakis, Vice President of Design Technology

Intel Corporation

"Sun has been a driving force in SystemVerilog from its inception. SystemVerilog can significantly improve the productivity of designers in the coming years, and this book is a comprehensive reference text for engineers who want to learn about SystemVerilog for their next generation designs."

— Sunil Joshi, Vice President of Software Technologies & Compute Resources

Sun Microsystems, Inc.

"SystemVerilog addresses the need for efficient and powerful modeling essential to support the complexity, size and scale of next generation hardware designs. This book explains how to use SystemVerilog effectively and provides numerous examples to illustrate how each of the language constructs can best be utilized."

— Chris Malachowsky, Co-Founder and Vice President of Hardware

NVIDIA Corp.

About the Author

Stuart Sutherland is a former editor with the Dictionary of Canadian Biography.

Product Details

  • File Size: 4999 KB
  • Print Length: 418 pages
  • Publisher: Springer US; 2nd edition (September 15, 2006)
  • Publication Date: September 15, 2006
  • Sold by: Amazon Digital Services LLC
  • Language: English
  • ASIN: B000WLU8EU
  • Text-to-Speech: Enabled
  • X-Ray:
  • Word Wise: Not Enabled
  • Lending: Not Enabled
  • Enhanced Typesetting: Not Enabled
  • Amazon Best Sellers Rank: #1,013,242 Paid in Kindle Store (See Top 100 Paid in Kindle Store)
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Customer Reviews

Top Customer Reviews

Format: Hardcover
(My review is about the 2006 2nd-edition, not the older 1st edition!)

In general, I agree with the other reviews. This book is written for an audience of Verilog designers, who know the Verilog language (and its limitations) all to well. The book covers Systemverilog's new features like, enum, struct, interfaces, etc., from the perspective of "how to write better RTL-code using Systemverilog instead of Verilog.' For example, it explains the pros/cons of the (Systemverilog) "interface" construct, vs a flat group of (Verilog) module-port declarations. The discussion helps designers appreciate RTL-coding from a (slightly) higher levle of abstraction.

You don't need a specific background (i.e. design-engineer) to benefit from this book; you just need a good familiarity with conventional Verilog.

As others have said, this book is not suitable as a reference. The paragraphs flow well, but it's hard to lookup an arbitrary topic from the index. So far, no hardcover-book can displace the official IEEE Systemverilog LRM as the best reference.

And since the book focuses on the 'design' (synthesizeable) aspect of Systemverilog, it doesn't cover non-synthesizeable language features (like classes, constrained random variables, etc.)
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Format: Hardcover Verified Purchase
I am using the book and getting value from it. the examples are not complete, but in a week I have scanned the book and had it open to review several times a day as I write and debug code.

On choosing which books to get to start with System Verilog: This one is focused on design, so has pointers on synthesizable descriptions and types. If you are doing verification you need both this and its companion, SystemVerilog for Verification: A Guide to Learning the Testbench Language Features by Chris Spear

You also need a verilog starter book, I may come back with an update on a recommendation.
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Format: Hardcover
I use SystemVerilog for test bench coding. Nice to see a revised edition to correct and improve the original. This book is fantastic: good examples, well thought out. The topics flow well and are well written. Don't waste your time or money with any other SV book - this is it.
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Format: Hardcover Verified Purchase
Not going to be elaborate on this review. Its a book not for beginners but for people who know SV and are already doing design. provides many case studies with examples. I wouldn't say this is a "must" book but its very well a good book.
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Format: Paperback Verified Purchase
This book is great for anyone who knows Verilog and wants to learn the design side of SystemVerilog. The book is very detailed but also easy to read. I strongly recommend it for all RTL designers and Architects who want to learn SV.
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