Customer Reviews

SystemVerilog for Design Second Edition: A Guide to Using SystemVerilog for Hardware Design and Modeling

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(My review is about the 2006 2nd-edition, not the older 1st edition!)

In general, I agree with the other reviews. This book is written for an audience of Verilog designers, who know the Verilog language (and its limitations) all to well. The book covers Systemverilog's new features like, enum, struct, interfaces, etc., from the perspective of "how to write better RTL-code using Systemverilog instead of Verilog.' For example, it explains the pros/cons of the (Systemverilog) "interface" construct, vs a flat group of (Verilog) module-port declarations. The discussion helps designers appreciate RTL-coding from a (slightly) higher levle of abstraction.

You don't need a specific background (i.e. design-engineer) to benefit from this book; you just need a good familiarity with conventional Verilog.

As others have said, this book is not suitable as a reference. The paragraphs flow well, but it's hard to lookup an arbitrary topic from the index. So far, no hardcover-book can displace the official IEEE Systemverilog LRM as the best reference.

And since the book focuses on the 'design' (synthesizeable) aspect of Systemverilog, it doesn't cover non-synthesizeable language features (like classes, constrained random variables, etc.)

I am using the book and getting value from it. the examples are not complete, but in a week I have scanned the book and had it open to review several times a day as I write and debug code.

On choosing which books to get to start with System Verilog: This one is focused on design, so has pointers on synthesizable descriptions and types. If you are doing verification you need both this and its companion, SystemVerilog for Verification: A Guide to Learning the Testbench Language Features by Chris Spear

You also need a verilog starter book, I may come back with an update on a recommendation.

Not going to be elaborate on this review. Its a book not for beginners but for people who know SV and are already doing design. provides many case studies with examples. I wouldn't say this is a "must" book but its very well a good book.

This book is great for anyone who knows Verilog and wants to learn the design side of SystemVerilog. The book is very detailed but also easy to read. I strongly recommend it for all RTL designers and Architects who want to learn SV.

I use SystemVerilog for test bench coding. Nice to see a revised edition to correct and improve the original. This book is fantastic: good examples, well thought out. The topics flow well and are well written. Don't waste your time or money with any other SV book - this is it.