SystemVerilog for Verification teaches the reader how to use the power of the new SystemVerilog testbench constructs plus methodology without requiring in-depth knowledge of Object Oriented Programming or Constrained Random Testing. The book covers the SystemVerilog verification constructs such as classes, program blocks, C interface, randomization, and functional coverage. SystemVerilog for Verification also reviews some design topics such as interfaces and array types. There are extensive code examples and detailed explanations. The book will be based on Synopsys courses, seminars, and tutorials that the author developed for SystemVerilog, Vera, RVM, and OOP. Concepts will be built up chapter-by-chapter, and detailed testbench using these topics will be presented in the final chapter. SystemVerilog for Verification concentrates on the best practices for verifying your design using the power of the language.
I was born near the Arctic Circle in Alaska, grew up in Anchorage, and have lived in Cocoa Beach, Wellesley, Ithaca NY (BSEE Cornell), and Madrid, Spain during the "transition" from dictatorship to democracy.
After college I worked on DECsim at Digital Equipment in the SEG/CAD group in Hudson, MA. That lasted until 1989 when mortgage payments forced me to look for a new job. I accepted a Field Application Engineer job with a small simulation company, Gateway Design Automation, but on the day I joined they merged with Cadence Design Systems. After too many reorganizations, I packed up and went to Viewlogic which was purchased by Synopsys in 1997.
When Synopsys bought System Science in 1998, I was in the first Vera class, learning about Hardware Verification Languages. I helped dozens of companies verify their designs with Vera and taught hundreds of customers. So when Synopsys donated Vera to Accellera to be the basis of SystemVerilog, I saw a great opportunity and helped create the first training, which eventually turned into the book SystemVerilog for Verification.
