The updated second edition of this book provides practical information for hardware and software engineers using the SystemVerilog language to verify electronic designs. The author explains methodology concepts for constructing testbenches that are modular and reusable. The book includes extensive coverage of the SystemVerilog 3.1a constructs such as classes, program blocks, randomization, assertions, and functional coverage. This second edition contains a new chapter that covers programs and interfaces as well as chapters with updated information on directed testbench and OOP, layered, and random testbench for an ATM switch.
I was born near the Arctic Circle in Alaska, grew up in Anchorage, and have lived in Cocoa Beach, Wellesley, Ithaca NY (BSEE Cornell), and Madrid, Spain during the "transition" from dictatorship to democracy.
After college I worked on DECsim at Digital Equipment in the SEG/CAD group in Hudson, MA. That lasted until 1989 when mortgage payments forced me to look for a new job. I accepted a Field Application Engineer job with a small simulation company, Gateway Design Automation, but on the day I joined they merged with Cadence Design Systems. After too many reorganizations, I packed up and went to Viewlogic which was purchased by Synopsys in 1997.
When Synopsys bought System Science in 1998, I was in the first Vera class, learning about Hardware Verification Languages. I helped dozens of companies verify their designs with Vera and taught hundreds of customers. So when Synopsys donated Vera to Accellera to be the basis of SystemVerilog, I saw a great opportunity and helped create the first training, which eventually turned into the book SystemVerilog for Verification.
