Testing of Digital Systems [Hardcover]

N. K. Jha (Author), S. Gupta (Author)

Book Description

Publication Date: May 15, 2003

Device testing represents the single largest manufacturing expense in the semiconductor industry, costing over $40 billion a year. The most comprehensive and wide-ranging book of its kind, Testing of Digital Systems covers everything you need to know about this vitally important subject. Starting right from the basics, the authors take the reader through every key area, including detailed treatment of the latest techniques such as system-on-a-chip and IDDQ testing. Written for students and engineers, it is both an excellent senior/graduate level textbook and a valuable reference.

Editorial Reviews

Book Description

As the complexity of modern digital systems increases, so does the need for ever more rigorous testing at all levels, from individual chips up to complete system architectures. This book is the most comprehensive introduction available to the range of techniques and tools used in digital testing. It covers every key topic, including fault simulation, CMOS testing, design for testability, and built-in self test. The book is aimed at graduate students of electrical and computer engineering, and is the most up-to-date reference volume on the market for practicing engineers.

About the Author

Niraj Jha is Professor of Electrical Engineering at Princeton University and head of the Center of Embedded System-on-a-Chip Design, where his current research is focussed on the synthesis and testing of these devices. He is a fellow of IEEE, associate editor of IEEE Transactions on VLSI Systems and The Journal of Electronic Testing: Theory and Applications (JETTA) and a recipient of the AT&T Foundation award and the NEC preceptorship award for research excellence.

Sandeep Gupta is an Associate Professor in the Department of Electrical Engineering at the University of Southern California, USA. He is Co-Director of the M.S. Program in VLSI Design, with research interests in the area of VLSI testing and design. He is a member of the IEEE.

Product Details

• Hardcover: 1016 pages
• Publisher: Cambridge University Press; 1 edition (May 15, 2003)
• Language: English
• ISBN-10: 0521773563
• ISBN-13: 978-0521773560
• Product Dimensions: 10.1 x 7.2 x 1.9 inches
• Shipping Weight: 4.8 pounds (View shipping rates and policies)
• Average Customer Review: 1.0 out of 5 stars  See all reviews (1 customer review)
• Amazon Best Sellers Rank: #1,144,071 in Books (See Top 100 in Books)

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Most Helpful Customer Reviews

5 of 7 people found the following review helpful:

1.0 out of 5 stars Difficult to Understand, September 23, 2007

By 

Aaron (Seattle, WA) - See all my reviews

This review is from: Testing of Digital Systems (Hardcover)

I starting reading this book with an open mind and thought I would like it. However, after the first chapter I began encountering unexplained notation and abbreviations that do not exist in the index. I have started finding many algorithms and concepts that leave me scratching my head - either the authors are brilliant or they've managed to pull together an impressive array of equations and explanations from research papers in an utterly incomprehensive manner (perhaps too much is crammed into one book?). My professor seems to love the notations and explanations, so maybe it's just me. Also, I don't understand why the authors need to introduce box symbols for digital gates (AND, NAND, etc.) when easily recognizable symbols already exist in the industry.