Engineering & Transportation

Sorry, this item is not available in
Image not available for
Color:
Image not available

To view this video download Flash Player

 
Sell Us Your Item
For a $8.55 Gift Card
Trade in
Have one to sell? Sell yours here
Tell the Publisher!
I'd like to read this book on Kindle

Don't have a Kindle? Get your Kindle here, or download a FREE Kindle Reading App.

Testing Semiconductor Memories: Theory and Practice [Hardcover]

A. J. Van De Goor
5.0 out of 5 stars  See all reviews (1 customer review)


Available from these sellers.


Free Two-Day Shipping for College Students with Amazon Student

Formats

Amazon Price New from Used from
Hardcover --  
Paperback --  
China
Engineering & Transportation Books
Discover books for all types of engineers, auto enthusiasts, and much more. Learn more

Book Description

September 1998 0471925861 978-0471925866
Comprehensive coverage of memory test problems at chip, array and board level is provided in this book. For each of these test levels a class of fault models is introduced along with tests for these models. The author also presents algorithms of relevant fault models, together with proofs of their correctness. Special attention is given to why a fault model belongs to a particular class and why it is of interest. A software package, suitable for use on IBM PCs and compatibles,is also available which consists of a set of memory test programs and a simulation package demonstrating how the algorithms are executed and the relationship of the algorithm with the memory.

Editorial Reviews

From the Publisher

As the size and density of semiconductor memories are increasing rapidly, testing them is becoming a major concern. This book tries to bring order to the vast amount of material published in the field by introducing a framework for ordering fault models and covering those test algorithms which are considered most efficient for finding the faults of each fault model. It presents memory test problems on the chip, array and board level, introducing fault models and tests for them at each of those levels.

Product Details

  • Hardcover: 512 pages
  • Publisher: John Wiley & Sons Inc (September 1998)
  • Language: English
  • ISBN-10: 0471925861
  • ISBN-13: 978-0471925866
  • Product Dimensions: 9.1 x 7.5 x 1.4 inches
  • Shipping Weight: 2.4 pounds
  • Average Customer Review: 5.0 out of 5 stars  See all reviews (1 customer review)
  • Amazon Best Sellers Rank: #3,211,875 in Books (See Top 100 in Books)

More About the Author

Discover books, learn about writers, read author blogs, and more.

Customer Reviews

5.0 out of 5 stars
(1)
5.0 out of 5 stars
4 star
0
3 star
0
2 star
0
1 star
0
Share your thoughts with other customers
Most Helpful Customer Reviews
1 of 3 people found the following review helpful
5.0 out of 5 stars The bibel of memory test March 2, 2004
Format:Paperback
Over 30% of today's designs implements embedded memories and continuously consumes more and more die area. While embedded memory presents significant system performance and cost reduction advantages, it brings its own testing issues. Test vector style tests are not suitable for verifying embedded memory arrays because it is too costly. This is because the time spent in the manufacturing tester grows exponentially as the embedded memory die area increases. Sometimes it is impossible to create a set of vectors that can detect all possible types of memory defect.
Implementing embedded memory built in self-test (BIST) can alleviate these problems. In simplistic terms, memory BIST is an on-chip utility that enables the execution of a proven set of algorithmic style verification tests directly on the memory array. These tests can be executed at the design's full operating frequency to prove the memory array operations and identify errors caused by silicon defects.
Embedded memories are the most dense components within a system-on-chip (SOC), accounting for up to 90% of its real estate.1 Memories also are the most sensitive to process defects, making it essential to thoroughly test them in the SOCs.
Because memories are used as test vehicles for monitoring the silicon process and improving its yield, extracting additional diagnostic data to determine the causes of failures now is required in the testing strategy. In addition to diagnosis, many embedded memories are designed with built-in redundancy, which provides spare rows and columns that can replace failing locations. Redundancy enables the manufacturer to repair a number of otherwise defective devices to ensure maximum production yield.
Characteristics of today's SOC designs include the following:
1.
Read more ›
Comment | 
Was this review helpful to you?
Search Customer Reviews
Search these reviews only

Sell a Digital Version of This Book in the Kindle Store

If you are a publisher or author and hold the digital rights to a book, you can sell a digital version of it in our Kindle Store. Learn more

Forums

There are no discussions about this product yet.
Be the first to discuss this product with the community.
Start a new discussion
Topic:
First post:
Prompts for sign-in
 



Look for Similar Items by Category