Testing Static Random Access Memories covers testing of one of the important semiconductor memories types; it addresses testing of static random access memories (SRAMs), both single-port and multi-port. It contributes to the technical acknowledge needed by those involved in memory testing, engineers and researchers. The book begins with outlining the most popular SRAMs architectures. Then, the description of realistic fault models, based on defect injection and SPICE simulation, are introduced. Thereafter, high quality and low cost test patterns, as well as test strategies for single-port, two-port and any p-port SRAMs are presented, together with some preliminary test results showing the importance of the new tests in reducing DPM level. The impact of the port restrictions (e.g., read-only ports) on the fault models, tests, and test strategies is also discussed. Features: -Fault primitive based analysis of memory faults, -A complete framework of and classification memory faults, -A systematic way to develop optimal and high quality memory test algorithms, -A systematic way to develop test patterns for any multi-port SRAM, -Challenges and trends in embedded memory testing.
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Editorial Reviews
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From the reviews: "Static random access memories (SRAMs) enjoy a strategic position in the microelectronic industry. … This book concentrates on the study of fault modeling, testing and test strategies for SRAMs. … The book provides a well-written coverage in the area of single-, two- and n-port SRAM testing, fault modeling, and simulation. It is well-organized and very timely. … The book promises to make valuable contribution to the education of graduate students … . I highly recommend this book … ." (Mile Stojcev, Microelectronics Reliability, Vol. 45, 2005)
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Inside This Book
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First Sentence:
Ultra large scale integrated (ULSI) circuits are an integral part of any modern electronic system. Read the first page Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
simultaneous read operations, total test length, sensitizing operations, transition write operation, second march element, sensitized fault, cell array faults, first march element, realistic fault models, data retention fault, impact the fault coverage, fault primitives, aggressor cell, coupling fault, functional fault models, two simultaneous operations, march elements, lrl lrl, new fault models, simultaneous write operations, mode sense amplifier, inductive fault analysis, memory cell array, single read operation, drd drd Key Phrases - Capitalized Phrases (CAPs): (learn more)
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Ultra large scale integrated (ULSI) circuits are an integral part of any modern electronic system. Read the first page Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
simultaneous read operations, total test length, sensitizing operations, transition write operation, second march element, sensitized fault, cell array faults, first march element, realistic fault models, data retention fault, impact the fault coverage, fault primitives, aggressor cell, coupling fault, functional fault models, two simultaneous operations, march elements, lrl lrl, new fault models, simultaneous write operations, mode sense amplifier, inductive fault analysis, memory cell array, single read operation, drd drd Key Phrases - Capitalized Phrases (CAPs): (learn more)
Oro Oro, Oro Owl New!
Books on Related Topics | Concordance | Text Stats Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Index | Back Cover | Surprise Me!
Citations (learn more)
This book cites 8
books:
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- Test Resource Partitioning for System-on-a-Chip (FRONTIERS IN ELECTRONIC TESTING Volume 20) by Vikram Iyengar in Front Matter
- Digital Systems Testing and Testable Design by Breuer Friedman in Back Matter
- Formal Equivalence Checking and Design Debugging (Frontiers in Electronic Testing) by Shi-Yu Huang in Front Matter
- Testing Semiconductor Memories: Theory and Practice by A. J. Van De Goor in Back Matter
- Semiconductor Memories: A Handbook of Design, Manufacture and Application by Betty Prince in Back Matter
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