From the Back Cover
“In this monumental new book, Tom Shanley pulls together 15 years of history of Intel’s mainline microprocessors, the most popular and important computer architecture in history. Shanley has a keen eye for the salient facts, and an outstanding sense for how to organize and display the material for easy accessibility by the reader. If you want to know what does this bit control, what does that feature do, and how did those instructions evolve through several generations of x86, this is the reference book for you. This is the book Intel should have written, but now they don’t have to.”
, Intel Fellow
The Unabridged Pentium 4 offers unparalleled coverage of Intel’s IA32 family of processors, from the 386 through the Pentium 4 and Pentium M processors. Unlike other texts, which address solely a hardware or software audience, this book serves as a comprehensive technical reference for both audiences. Inside, Tom Shanley covers not only the hardware design and software enhancements of Intel’s latest processors, he also explains the relationship between these hardware and software characteristics. As a result, readers will come away with a complete understanding of the processor’s internal architecture, the Front Side Bus (FSB), the processor’s relationship to the system, and the processor’s software architecture.
Essential topics covered include:
- Goals of single-task and multi-task operating systems
- The 386 processor—the baseline ancestor of the IA32 processor family
- The 486 processor, including a cache primer
- The Pentium processor
- The P6 roadmap, P6 processor core, and P6 FSB
- The Pentium Pro processor, including the Microcode Update feature
- The Pentium II and the Pentium II Xeon and Celeron processors
- The Pentium III and the Pentium III Xeon and Celeron processors
- The Pentium 4 processor family
- The Pentium M processor
- Processor identification, System Management Mode, and the IO and Local APICs
An “at-a-glance” table of contents allows readers to quickly find topics ranging from 386 Demand Mode Paging to Pentium 4 CPU Arbitration.
The accompanying CD-ROM contains 16 extra chapters.
Whether you design software or hardware or are responsible for system maintenance or customer support, The Unabridged Pentium 4 will prove an invaluable reference to the world’s most widely used microprocessor chips.
MindShare’s PC System Architecture series is a crisply written and comprehensive set of guides to the most important PC hardware standards. Books in the series are intended for use by hardware and software designers, programmers, and support personnel.
One of the leading technical training companies in the hardware industry, MindShare, Inc., provides innovative courses for dozens of companies, including HP, AMD, IBM, and Compaq. Through these classes and by writing the highly regarded PC System Architecture Series for Addison-Wesley, MindShare trainers emphasize the relationships of hardware subsystems to each other as well as the relationship between software and hardware.
Excerpt. © Reprinted by permission. All rights reserved.
The IA32 Architecture Specification
There is no document that is officially referred to as the IA32 Architecture Specification. Rather, it consists of the three volume set consisting of:
- IA-32 Intel® Architecture Software Developer’s Manual Volume 1: Basic Architecture.
- IA-32 Intel® Architecture Software Developer’s Manual Volume 2: Instruction Set Reference.
- IA-32 Intel® Architecture Software Developer’s Manual Volume 3: System Programming Guide.
While the specification defines the register set, the instruction set and the software exceptions, it does not include the specific methodologies used to implement a specific processor. For example, the following design decisions are outside the scope of the specification:
- Whether or a processor design includes caches and, if so, the number of, size of, and architecture of the caches.
- Whether or not a processor design includes one or more TLBs and, if so, the number of, size of, and architecture of the TLBs.
- The type of bus that connects the processor to the system.
- The number and types of instruction execution units.
The Pentium® 4 Is the Sum of Its Ancestors
The Pentium® 4 processor embodies all of the software characteristics that were incrementally introduced over the years since the introduction of the 386 processor. This software environment evolution consists of three elements:
- The evolution of the register set.
- The evolution of the instruction set.
- The evolution of the software exceptions.
There is real value in understanding how the architecture has grown over the years.
The CD that accompanies the book contains an additional 16 chapters of material that could not be included in the book due to binding constraints. This material is provided in the form of a PDF file.
The reader should keep in mind that MindShare’s book series often deals with rapidly evolving technologies. This being the case, it should be recognized that the book is a “snapshot” of the state of the targeted technology at the time that the book was completed. We attempt to update each book on a timely basis to reflect changes in the targeted technology, but, due to various factors (waiting for the next version of the spec to be “frozen,” the time necessary to make the changes, and the time to produce the books and get them out to the distribution channels), there will always be a delay.
The Specification Is the Final Word
As with all of our books, this book represents the author’s interpretation of the specification. When in doubt, the Intel specification is the final word.
Bits Versus Bytes Notation
All abbreviations for “bits” use lower case. For example:
- 2.5Gb/s = 2.5 Gigabits per second.
- 2Mb = 2 Megabits.
All references to “bytes” are specified in upper case. For example:
- 10MB/s = 10 Megabytes per second.
- 2KB = 2 Kilobytes.
- “lsb” refers to the least-significant bit.
- “LSB” refers to the least-significant byte.
- “msb” refers to the most-significant bit.
- “MSB” refers to the most-significant byte.
Bit Fields (Logical Groups of Bits or Signals)
In many cases, bit fields are documented as 15:8, with this example referring to bits 8 through 15.
Each signal name is either followed by the “#” suffix or not. The “#” suffix indicates that the signal is asserted (i.e., active) when driven to an electrical low. Conversely, a signal name without the suffix is asserted when at the electrically high level. Some examples:
- SMI#, RESET# and MCERR# are asserted when low.
- BOOTSELECT and PWRGOOD are asserted when high.
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