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Timing (Information Technology: Transmission, Processing and Storage)
 
 
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Timing (Information Technology: Transmission, Processing and Storage) [Hardcover]

Sachin Sapatnekar (Author)

Price: $179.00 & this item ships for FREE with Super Saver Shipping. Details
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Book Description

Information Technology: Transmission, Processing and Storage June 2, 2004
With the advent of nanometer technologies, circuit performance constraints are becoming ever more stringent. In this context, automated timing analysis and optimization becomes imperative for the design of high-performance circuits that must satisfy a demanding set of constraints. Timing overviews the state of the art in timing analysis and optimization, and is intended to serve as a compendium that can provide an introduction to the uninitiated reader, as a ready reference for a practitioner, or as a source for the accomplished researcher. A comprehensive overview of the basics of timing analysis is provided, and this is augmented with techniques that incorporate physical effects arising in deep submicron and nanometer technologies. The book provides an in-depth treatment of the analysis of interconnect systems, static timing analysis for combinational circuits, timing analysis for sequential circuits, and timing optimization techniques at the transistor and layout levels. The intended audience includes CAD tool developers, graduate students, research professionals, and the merely curious.

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Editorial Reviews

Review

From the reviews: "The book is highly recommended to CAD tool developers, graduate students, researchers in the timing analysis field as well as digital designers interested in finding out the underlying principles employed by the tools used in digital design." (Ion-Constantin Tesu, Zentralblatt MATH, Vol. 1059 (10), 2005)

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Inside This Book (learn more)
First Sentence:
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Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
clock network construction, area retiming problem, combinational stage, long path violation, ratioing constraints, generalized posynomial, long path constraints, fall arrival times, mirror vertices, short path constraints, target clock period, minimum area retiming, purely combinational path, retiming solutions, skew optimization, optimal clock period, statistical timing analysis, retimed circuit, aggressor alignment, specified clock period, statistical static timing analysis, timing allowance, saturated ramp, domino gate, transistor sizing problem
Key Phrases - Capitalized Phrases (CAPs): (learn more)
Computer-Aided Design, Design Automation Conference, International Conference, Backward Euler, Forward Euler, International Symposium, International Workshop, New York, Journal of Solid-State Circuits, Computer Design, Kluwer Academic Publishers, Test Symposium, Englewood Cliffs, Europe Conference, Monte Carlo, Technical Report
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