This work focuses on optimizing the timing of large-scale, high-performance, digital synchronous systems. A particular emphasis is placed on algorithms for non-zero clock skew scheduling to improve the performance and reliability of VLSI circuits. This research monograph answers the need for a broad introduction to state-of-the-art clock skew scheduling algorithms from a circuit, graph, and mathematical optimization background. A detailed description of an original quadratic programming (QP) formulation of the clock skew scheduling problem is provided along with an analysis of optimal computer solution techniques. It contains sufficient detail for the advanced CAD algorithm developer, researcher and graduate student. Furthermore, with the material provided on timing properties and optimization, those readers with less background should also benefit from this book.
FREE Two-Day Shipping for students on millions of items. Learn more |
Book Description
Editorial Reviews
From the Back Cover
Timing Optimization Through Clock Skew Scheduling focuses on optimizing the timing of large scale, high performance, digital synchronous systems. A particular emphasis is placed on algorithms for non-zero clock skew scheduling to improve the performance and reliability of VLSI circuits. This research monograph answers the need for a broad introduction to state-of-the-art clock skew scheduling algorithms from a circuit, graph, and mathematical optimization background. A detailed description of clock skew scheduling application on edge-triggered and level-sensitive circuits, synchronized with single and multi-phase clocking schemes, and formulated as linear programming (LP) and quadratic programming (QP) formulations are provided along with an analysis of optimal computer solution techniques. Theoretical limits of improvement in clock frequency through clock skew scheduling are highlighted. Hints and a preliminary implementation of a parallel skew scheduling application are also included. Timing Optimization Through Clock Skew Scheduling contains sufficient detail for the advanced CAD algorithm developer, researcher and graduate student. Furthermore, with the material provided on timing properties and optimization, those readers with less background can also benefit from this book.
--This text refers to an alternate
Hardcover
edition.
Product Details
Would you like to update product info or give feedback on images?
|
More About the Author
Discover books, learn about writers, read author blogs, and more.
Customer Reviews
|
There are no customer reviews yet.
|
|||
|
Video reviews
|
Inside This Book
(learn more)
Browse and search another edition of this book.
Browse and search another edition of this book.
Key Phrases - Statistically Improbable Phrases (SIPs):
(learn more)
clock skew scheduling, skew scheduling problem, local data path, clocking technology, data propagation times, effective path delay, data path cycles, skew scheduling algorithms, clock skew circuits, clock schedule tcd, clock skew schedule, data path loops, clocking technologies, clock skew values, zero clock skew, clock skew systems, period minimization problem, clock tree topology, reconvergent paths, data path system, physical design flow, delay insertion, clock period achievable, target clock period, minimum clock period Key Phrases - Capitalized Phrases (CAPs): (learn more)
Springer Science, Business Media, Timing Properties of Synchronous Systems, Experimental Results, Multi-Phase Level-Sensitive Circuits, Single-Phase Path, Data Out, Practical Considerations, Software Implementation, Computational Analysis, Data Logic, Read-In Fig, Multi-Phase Path, Clock Planning, Modified Circuits, Continuous Delay Models Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Index | Surprise Me!
clock skew scheduling, skew scheduling problem, local data path, clocking technology, data propagation times, effective path delay, data path cycles, skew scheduling algorithms, clock skew circuits, clock schedule tcd, clock skew schedule, data path loops, clocking technologies, clock skew values, zero clock skew, clock skew systems, period minimization problem, clock tree topology, reconvergent paths, data path system, physical design flow, delay insertion, clock period achievable, target clock period, minimum clock period Key Phrases - Capitalized Phrases (CAPs): (learn more)
Springer Science, Business Media, Timing Properties of Synchronous Systems, Experimental Results, Multi-Phase Level-Sensitive Circuits, Single-Phase Path, Data Out, Practical Considerations, Software Implementation, Computational Analysis, Data Logic, Read-In Fig, Multi-Phase Path, Clock Planning, Modified Circuits, Continuous Delay Models Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Index | Surprise Me!
Tag this product(What's this?)Think of a tag as a keyword or label you consider is strongly related to this product.
Tags will help all customers organize and find favorite items. |
Sell a Digital Version of This Book in the Kindle Store
If you are a publisher or author and hold the digital rights to a book, you can sell a digital version of it in our Kindle Store.
Learn more
Customer Discussions
|
This product's forum
Active discussions in related forums
Search Customer Discussions
|
Related forums
|
