Customer Reviews

VHDL Coding Styles and Methodologies

5 star:		(5)
4 star:		(0)
3 star:		(1)
2 star:		(0)
1 star:		(0)

 

 

As the title said, this book has a lot of good examples on how to write VHDL code with good coding styles. Most of the good coding style tips in the book make sense and I use it in my work. However, I don't think this is a good book to learn VHDL. The syntax is explained in the same style as the VHDL Language Reference Manual, which is very dry. For example: the author explained the syntax of for loop like this: loop_statement ::= [loop_label][iteraction_scheme] loop sequence_of_statements end loop [loop_label]. I learned some VHDL constructs from this book but they are not very clear. After finished reading the book, I still feel something missing and I need to refer to other VHDL books to fill up the gap. The author also spent only a few pages on synthesis and the index is poorly organized. With all of these and combined with its ridiculous price, I would recommend to borrow the book from library if you want some tips on good coding styles. But I won't recommend to buy it if you want to learn basic VHDL, because the book is no good for that purpose.

This is an excellent book for the practicing engineer who wants a real world example. The book has many examples of code which will compile and work. In addition it has recommendations on best practices ( 2 thumbs up) and worst practices (2 thumbs down) with a rational for why you would want to follow the recommended practice. It also makes clear distinction between sythesizable code, and behavioral code. Compared with the other books which are heavy on the language semantics (and examples that won't compile) this is a much more usable book. The hardware desiner will find this to be the best book they have.

This book has just become my number one book to recommend to the students of the VHDL classes that I teach. It is very well written and the book is loaded with VHDL examples demonstrating the various constructs, statements and issues. In example 5.5.1.2, the author does the best job I have ever seen of explaining the difficult subject of "Projected Output". The subjects are frequently associated to the specifications found in the Language Reference Manual. When there is a linking issue between two or more design elements, the linking is clearly demonstrated with examples. The only negative is that the author spends far too much time and book space describing ways to "Enhance Readibility" or documenting your design--which is always a personal preference. But still, a five star book.

An indispensable book. He gets your mind thinking in VHDL coding. Not only in what you write, but how you write it for structure, consistancy and readability. Full of coding examples and test benches for almost every aspect of VHDL including the source code on CD. Ben's ideas for coding styles really gives a consistant look to all my code. Coding he gets into the nuts and bolts of VHDL. Types, arrays, functions, aggregates, cases, generics, packages, concurrent, sequential, parameters formal and actual ..., the rationals explain why and examples examples examples. This book sits with me at all times.

This is a very good reference book for checking coding styles and syntax for VHDL. There are several books that teach the basics of how to write VHDL code, but this book shows you best practices for doing a good design in your projects. This book is a must have for anyone who wants to become a proficient VHDL designer who can produce quality designs.

This is the best of 4 books I purchased on the subject of VHDL, by a factor of 10. The price took me by surprise but it was readily available through the third party link. Buy this one and you won't need any of the others. If I would have purchased this one a year ago it would have saved me much grief.