VHDL Design Representation and Synthesis (2nd Edition) [Paperback]

James R. Armstrong (Author), F. Gail Gray (Author)

Book Description

ISBN-10: 0130216704 | ISBN-13: 978-0130216700 | Publication Date: April 9, 2000 | Edition: 2

For senior/graduate-level courses in Advanced Digital Design and Advanced Digital Logic in departments of electrical engineering, computer engineering, and computer science.Intended to teach a synthesis-based approach to design using a hardware description language (i.e., VHDL), this text focuses on the synthesis process in how to translate VHDL descriptions into gate level logic. It teaches the VHDL language in detail, describes modeling at three different levels of abstraction (algorithmic, data flow, and gate level), and explains the ASIC Design Process. Illustrations of synthesis with standard cell libraries and FPGAs are given using Synopsys and Xilinx tools.

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Preface

The purpose of this book is to integrate hardware description languages into the digital design process at all levels of abstraction. There are two main steps in this process: (1) development of a hardware description language model and (2) synthesis of the model into an ASIC logic circuit or FPGAs. In teaching this process, we use VHDL, the VHSIC Hardware Description Language. VHDL, whose development began in 1983 under DOD sponsorship, was further developed by the IEEE and released as IEEE Standard 1076 in 1987. Further improvements were incorporated since then and the language was re-released as an updated standard in 1993. Since that time, VHDL has evolved into a de facto industry standard for hardware description languages. In the opinion of the authors, it has the most comprehensive set of modeling constructs available in any hardware description language. For these reasons, VHDL was chosen as the base language for this book. We explore the language in an in-depth, unified manner.

Most books currently on the market that treat hardware description languages, particularly VHDL, are either: (1) language texts that cover the VHDL language thoroughly, but do not show how to integrate the language into the digital design process, or (2) logic design books that primarily use VHDL models as simulation tools to validate designs that are produced in the classical manner. This book fully integrates VHDL into the design process starting with a high-level executable model that provides an unambiguous, executable version of the specification, and concluding with a gate-level implementation.

In this book, synthesis is viewed as a multistep process, beginning with an English description which is transformed first into VHDL and then from VHDL into a circuit schematic. We discuss synthesis from two viewpoints: 1) the mappings: emphasis is placed on understanding the relationship between VHDL language constructs and the implied logic circuit. A full chapter is devoted to correct modeling style for synthesis; 2) the tools: we illustrate the synthesis process using two very popular tool sets, the Synopsys Design Analyzer and Compiler (for ASICs) and the Xilinx Foundation Series (for FPGAs). Since ASICs and FPGAs are the targets, a chapter is devoted to these technologies. The book also contains a chapter illustrating the complete top-design design process from specification to logic synthesis.

This book is written for three main educational purposes: (1) for a second course in logic design for undergraduate students in Electrical Engineering, Computer Engineering, and Computer Science; (2) for a graduate course dealing with hardware description languages and other design aids; and (3) for practicing engineers who wish to learn about design with hardware description languages. Thus the assumed background for the book is (1) a basic course in computer organization and logic design and (2) some knowledge of high-level languages, such as C, C++, or JAVA.

The authors use the text in a course, which is the second course in a logic design sequence. The students are either juniors in Computer Engineering, for whom the course is required, or Electrical Engineering seniors, for whom the course is an elective. In this semester length course we cover Chapters 1, 2, 3, 4, 5, 9, 10, and 11. The emphasis is on developing VHDL models in a conservative algorithmic style that can be synthesized. To support this in the laboratory, we use a PC version of ViewLogic, Inc.'s Workview for VHDL modeling and simulation and schematic capture. Xilinx software and XS40/XTEND boards are used for FPGA synthesis. We also em-ploy System View from Elanix to provide for high-level design of digital filters. Workstation-based Synopsys tools are used for ASIC synthesis. All students in our department have their own PCs, so the use of a PC-based system such as Workview has been effective in being able to serve the large number of students we normally teach in our second digital design course. For this same reason, we use telnet and dc_shell scripts for Synopsys synthesis. Typical assignments include:

An introductory assignment to familiarize students with Workview's VHDL modeling, simulation and schematic capture environment. An assignment to develop and simulate a single VHDL behavioral model. An assignment to develop a model of a counter, or some similar circuit. VHDL behavioral models are developed for counter flip-flops and gates, and the schematic capture capability of Workview is used to construct the structural model of the counter. An assignment to translate a system description is first translated into a VHDL behavioral model which is simulated. This is typically a state machine such as an interface protocol, a vending machine, or a traffic light controller. An introductory tutorial to the Xilinx Foundation Series Software. An assignment to implement a small circuit in both Synopsys ASIC logic and FPGAs and compare speed of execution. A fairly complicated FPGA project such as a booth multiplier, calculator, small processor, digital filter, or graphics display. For the filter, the codec on the XSTEND board is used for A/D and D/A comversion. The Xilinx filter code is developed using System View. The graphics display displays a pattern stored in RAM on a VGA monitor.

If used for a graduate course, the entire book can be covered in one semester. In such a course, one can cover the broad range of constructs in the language and examine in detail the language semantics for both simulation and synthesis. In our graduate course at Virginia Tech, we synthesize with Synopsys and validate synthesized models. We study ways to control the synthesis to achieve optimum circuits in a delay or area sense. High-level modeling tools such as Express VHDL, SPW, and System View are also covered. A comparison is done between VHDL and Verilog.

For this course, the student's laboratory assignments include:

An assignment to develop and simulate a single VHDL behavioral model. An assignment to develop a model of a counter or some similar circuit. VHDL behavioral models are developed for counter flip-flops and gates, and then a VHDL structural model is developed for the whole system. An assignment involving complex data types, e.g., using array aggregates and record types to implement a tabular representation of a finite state machine. A system modeling assignment that involves the use of bus resolution and bus protocols. This system employs the IEEE 9 valued logic system. Examples include the URISC processor system in Chapter 6 or a histogram construction system for image processing. An assignment where a model is written, simulated, and synthesized using both VHDL and Verilog and comparison's made A semester project where the students model a system of their choice. One can choose projects, which stretch the language, i.e., involve applications that are not typical, such as modeling parallel processing systems or modeling systems which are not digital.

The book contains hundreds of VHDL models and code fragments. All code has been analyzed, and simulated, and synthesized (where required), using the Synopsys VHDL system. The only exception to this is the VHDL 93 code. In addition, the text contains over 300 homework problems with a wide range of difficulty. Types of problems include short answer questions, simple design problems, complex system design problems involving design, modeling, and simulation, and problems that require a study of a design or design tool issue. Some problems in this latter category would make good thesis projects!

Accompanying the book is a CD-ROM. On the CD are: 1) source files for all VHDL code in the book, 2) a set of projects accompanied by supporting data command files, and 3) packages to support common design paradigms. Problem and project solutions and Power Point lecture slides are available to instructors who adopt our text for classroom use.

From the Back Cover

VHDL Design Representation and Synthesis, Second Edition is an exceptionally clear, thorough, and up-to-date introduction to today's leading approach to hardware design: synthesis using a hardware description language and today's leading synthesis tools. Armstrong and Gray begin with an introduction to structured design, and a unified explanation of the VHDL language and its key constructs. Next, they introduce the modeling process step by step, using many examples at varying levels of abstraction, and demonstrate techniques designed to maximize both simulation efficiency and compatibility with synthesis tools.

• Design tools: editors, simulators, checkers, analyzers, optimizers, and synthesizers
• VHDL: major constructs, lexical description, source files, data types, data objects, statements, and advanced features
• Fundamental VHDL modeling techniques: propagation and time delay, concurrency, scheduling, combinational logic, sequential logic, and primitives
• Integrating VHDL into the design flow, from executable specifications at the algorithmic level through implementations at the gate or cell level
• Modling PLDs, gate arrays, FPGAs (using Xilinx tools) and standard cells (using Synopsys tools)

This edition contains extensive new coverage of multilevel modeling, design with standard parts and ASICs data and control unit design, modeling for synthesis, and more. Review problems are included in each chapter, and over 300 references are provided. If you intend to design with VHDL, this is the book to start with.

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Product Details

• Paperback: 651 pages
• Publisher: Prentice Hall; 2 edition (April 9, 2000)
• Language: English
• ISBN-10: 0130216704
• ISBN-13: 978-0130216700
• Product Dimensions: 9.1 x 7.2 x 1.4 inches
• Shipping Weight: 2.2 pounds (View shipping rates and policies)
• Average Customer Review: 3.3 out of 5 stars  See all reviews (3 customer reviews)
• Amazon Best Sellers Rank: #420,545 in Books (See Top 100 in Books)

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6 of 6 people found the following review helpful:

4.0 out of 5 stars A complete treatment, March 6, 2001

By 

C. McManis "Chuck McManis" (Sunnyvale, CA USA) - See all my reviews
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This review is from: VHDL Design Representation and Synthesis (2nd Edition) (Paperback)

This is a good book to get if you want to know what is involved with designing chips today using VHDL. It starts slowly, first establishing a taxonomy for the design process and very carefully defining its terms, then picks up as it moves into more depth. Combined with a good book dedicated to synthesis and a VHDL language reference (I recommend Chang for the former, Ashenden for the latter) you can come away with a very good understanding of VHDL and its uses.

Things that would have made it better are appendices with the NUMERIC_STD libraries and STD_LOGIC libraries detailed. A bit more depth in the synthesis area and some answers to at least some of the chapter questions in the back. Thus if you are teaching yourself VHDL as I am you will need to talk to a VHDL expert to verify your understanding.

With all that being said, I have no reservations recommending this book. You can probably skip chapters 1 & 2 if you are not a beginner and jump in at chapter 3. The use of comercially available FPGA design boards was a plus as well since I could "follow along" with the examples. Now if I could only find the student guide/lab book ...

2 of 2 people found the following review helpful:

1.0 out of 5 stars Find a better book!, March 31, 2009

By 

Steven Mott "smashedapples" (Nebraska, USA) - See all my reviews
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This review is from: VHDL Design Representation and Synthesis (2nd Edition) (Paperback)

This is a piss poor book. There are two main ways in which this book is inadequate: the physical makeup of the book itself, and the content of the book.

Physical Book
My book (along with a few friends from class) is very poorly put together. The binding is very rigid. This means that you have to break the binding in order to get the book to lay open. It looks like the publisher bound the inside pages of the book with one type of glue, then slapped the cover on with an excessive amount of a very stiff glue that does not allow the binding to flex at all.

The figures all look like they were scanned in off of a piece of paper on the worlds lowest quality scanner (they might have even been faxed), then reprinted in the book.

The printer used to print the book must have actually been a low quality photocopier because things that should be solid black are blotchy and unevenly printed.

On the first page of the book, it tells you that it used to come with a CD. Now it's been replaced with a general reference to a website that is difficult to navigate. The website it directs you to isn't for the book, it's for the publisher. In order to find the book, I suggest typing the ISBN number into the search box. Then you have to figure out how to convince it that you already bought the book and are trying to get to the CD contents.

Content
There are more than too many typographical errors for a competent editor to have looked at this book. Also, a lot of the code examples given have incorrect syntax or semantics. The book claims it was copyrighted in 2000, but doesn't list previous copyrights. I would be willing to bet the original book was copyrighted around 1990.

The problems included with the chapters get very in depth and lengthy (and downright stupid). Unfortunately for the book, I have an incompetent professor who assigns problems without looking into the amount of effort required. We've been given assignments where we're expected to design a processor in only a week.

Summary
If this book is required for your class, I feel sorry for you. You probably should buy the book so you can do the homework the professor assigns. If you're looking for a reference for your personal use, I suggest going elsewhere.

2 of 18 people found the following review helpful:

5.0 out of 5 stars Wonderful Book for Electronic Engineer, May 13, 2000

By A Customer

This review is from: VHDL Design Representation and Synthesis (2nd Edition) (Paperback)

For the new beginner or senior engineer in electronic field, learn this new knowlegde is essential.