Customer Reviews

VHDL For Designers

5 star:		(2)
4 star:		(2)
3 star:		(1)
2 star:		(0)
1 star:		(0)

 

 

This is the book one should have who is doing something or anything in VHDL. Previously I had two books but those were filled with unnecessary explaination and nonsense examples. This book explain the facts to the point with plenty of examples. I think that it best for the startup and also for the experienced peoples for their reference.

I guess I was looking for a different book. I'm already quite familiar with hardware design, so I wasn't looking for a book to teach me that. I already have the IEEE VHDL standard document, but that's like reading a phone book. I wanted a readable handbook of the VHDL language - I never found that, so I settled for "VHDL for Designers" instead.

I come from a software background, programming in the large. I was looking for a book to teach me the language. For a programmer, that includes the record types (like C structs), 'generate' and 'generic' for parameterizing my design, recommended style for combining operator overloads with component definitions, proper use of libraries, packages, and multiple architectures, and so on.

This book is just the baby steps of VHDL. It's very focussed on its examples, and seems to give just enough VHDL for each example. It's OK for design at the "Hello world" level, but not much past that. It has most of the basic language constructs, but shallow discussion of them. The organization doesn't really lend itself to use as a language handbook.

Still, it does cover the basics. I'll just have to tough it out for the rest of the language. I still use the book, but I'm still looking for a better one.

I learned VHDL and developed a number of working designs using this book. It features many examples which may be used as skeleton for design blocks.

It does not teach theory of digital design; it demonstrates how to implement design in VHDL so that it can be synthesized.

This book covers the basic features of VHDL, but the explanation of some of the language features is a little thin. Sometimes, the book reads like a math text book that is full of proofs, but very little explanation of the proof (remember those books?). A reader who has some familiarity with VHDL will get more out of this book than someone who is just learning VHDL for the first time. However, the book does have some good VHDL examples which makes it a useful text.

Really i enjoyed reading this book.now i got confidence well on vhdl.The book is very well defined to the point. Previously I had two books but those were filled with unnecessary explaination and nonsense examples. This book explain the facts to the point with plenty of examples. I think that it best for the startup and also for the experienced peoples for their reference.