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VLSI Test Principles and Architectures: Design for Testability (The Morgan Kaufmann Series in Systems on Silicon)
 
 

VLSI Test Principles and Architectures: Design for Testability (The Morgan Kaufmann Series in Systems on Silicon) [Hardcover]

Laung-Terng Wang (Author), Cheng-Wen Wu (Author), Xiaoqing Wen (Author)
5.0 out of 5 stars  See all reviews (1 customer review)

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Book Description

0123705975 978-0123705976 July 21, 2006 1
This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.

· Most up-to-date coverage of design for testability.
· Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books.
· Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
· Lecture slides and exercise solutions for all chapters are now available.
· Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

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VLSI Test Principles and Architectures: Design for Testability (The Morgan Kaufmann Series in Systems on Silicon) + System-on-Chip Test Architectures: Nanometer  Design for Testability (Systems on Silicon) + Electronic Design Automation: Synthesis, Verification, and Test (Systems on Silicon)
Price For All Three: $192.19

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Editorial Reviews

Review

In the era of large systems embedded in a single system-on-chip (SOC) and fabricated continuously shrinking technologies, it is important to ensure correct behavior of the whole system. Electronic design and test engineers of today have to deal with these complex and heterogeneous systems (digital, mixed-signal, memory), but few have the possibility to study the whole field in a detailed and deep way. This book provides an extremely broad knowledge of the discipline, covering the fundamentals in detail, as well as the most recent and advanced concepts.

Michel Renovell, Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier (LIRMM), Montpellier, France

This book combines in a unique way insight into industry practices commonly found in commercial DFT tools but not discussed in textbooks, and a sound treatment of the future fundamentals. The comprehensive review of future test technology trends, including self-repair, soft error protection, MEMS testing, and RF testing, leads students and researchers to advanced DFT research.

Hans-Joachim Wunderlich, University of Stuttgart, Germany


Recent advances in semiconductor manufacturing have made design for testability (DFT) an essential part of nanometer designs. I am pleased to find a DFT textbook of this comprehensiveness that can serve both academic and professional needs.

Andre Ivanov, University of British Columbia, Canada

This is the most recent book covering all aspects of digital systems testing. It is a "must read" for anyone focused on learning modern test issues, test research, and test practices.

Kewal K. Saluja, University of Wisconsin-Madison


By covering the basic DFT theory and methodology on digital, memory, as well as analog and mixed-signal (AMS) testing, this book stands out as one best reference book that equips practitioners with testable SOC design skills.

Yihe Sun, Tsinghua University, Beijing, China

Book Description

The most up-to-date coverage available of VLSI Testing and Design-for-Testability!

Product Details

  • Hardcover: 808 pages
  • Publisher: Morgan Kaufmann; 1 edition (July 21, 2006)
  • Language: English
  • ISBN-10: 0123705975
  • ISBN-13: 978-0123705976
  • Product Dimensions: 9.4 x 8.1 x 2.1 inches
  • Shipping Weight: 4 pounds (View shipping rates and policies)
  • Average Customer Review: 5.0 out of 5 stars  See all reviews (1 customer review)
  • Amazon Best Sellers Rank: #536,920 in Books (See Top 100 in Books)

 

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4 of 5 people found the following review helpful:
5.0 out of 5 stars Practical Book, November 11, 2006
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Darth Vadar (Silicon Valley, California) - See all my reviews
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This review is from: VLSI Test Principles and Architectures: Design for Testability (The Morgan Kaufmann Series in Systems on Silicon) (Hardcover)
This is a great book for Test/DFT engineers and EDA engineers developing test tool. It gives a thorough review of lot of concepts and techniques employed in practice which cannot be found if you look at a general testing book. This also makes it an excellent resource to prepare for interviews.
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Inside This Book (learn more)
Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
linear decompressor, deductive fault simulation, scan design rules, fault coverage goal, available spare rows, failing syndrome, sequential fault simulation, untestable faults, bridging fault diagnosis, fault descriptors, nanometer age, transition count testing, memory access commands, scan extraction, adjacent scan cells, analog test buses, extended backward implications, redundancy analysis algorithms, scan input pin, test data volume, failing chip, space compactor, compressed stimulus, small delay defects, statistical fault analysis
Key Phrases - Capitalized Phrases (CAPs): (learn more)
Test Conf, Test Symp, Test Comput, Design Automation Conf, New York, Europe Conf, Computer Design, Fault-Tolerant Computing, John Wiley, Kluwer Academic, Repeat Problem, Mentor Graphics, Prentice Hall, Shift Window Capture Window Shift Window, Agilent Technologies, Solid-State Circuits, Custom Integrated Circuits Conf, Intentionally Left Blank, Palo Alto, Semiconductor Industry Association, Texas Instruments, Cambridge University Press, Circuits Syst, Digest of Papers, San Jose
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