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We see a prevalence of low power designs in Japan and a strong need for a comprehensive verification methodology to tape out such designs with confidence. VMM-LP is the answer to this market need and completely and elegantly addresses all aspects of low power verification. The book covers what is needed to verify low power designs and get it right the first time around.
Nobuyuki Nishiguchi, Vice President and General Manager, Development Department 1
STARC (Semiconductor Technology Academic Research Center)
The task of verifying low power designs presents a significant challenge for today's verification engineers, as most are not yet well-trained on low power concepts. The Verification Methodology Manual for Low Power is a timely and valuable resource that addresses all aspects of low power verification, providing detailed rules and guidelines.
Jianfeng Liu, Senior Low Power Verification Methodology Engineer
Because power consumption is one of the most critical factors of today s SoCs for mobile applications, the ability to accurately verify low power functionality is essential to achieving first-pass silicon success. The Verification Methodology Manual for Low Power is a comprehensive collection of necessary and reliable techniques that should help simplify and accelerate the complex task of verifying power-managed designs.
Ying-Chih Yang, Technical Director of Home Entertainment Products
Low power has been elevated to a primary design consideration and companies have been forced to deal with the complex verification issues associated with these design practice without much in the way of tool or methodology help. This book provides a key piece of that solution, with very helpful guidance that not only builds upon the existing VMM, but provides a firm foundation into sound techniques to ensure that no problems exist in the power control circuitry.
Brian Bailey, Independent Functional Verification and ESL Consultant
Being able to create a power control architecture is more than just having something that looks pretty on paper and, theoretically, meets your power targets. The VMM-LP provides clear insight into the pitfalls and practicality issues for both the design and verification of low power systems. This handy volume comes with specific examples of design and verification issues that have been seen in actual chips. Its rules and recommendations will help move the electronics industry into a much greener future.
David Wheelock, SoC Power Architect
Low power requirements have caused a paradigm shift for the entire semiconductor ecosystem. Lacking an open, codified and documented methodology, accurate and comprehensive verification of low power designs has been a black art and a productivity drain. With its methodical and guidebook style approach, the VMM-LP provides a clear blueprint for successful verification of low-power designs this one is a keeper.
Dr. Ed Huijbregts, Vice President of Product development
Magma Design Automation --Synopsys
Mr. Jadcherla holds a Bachelor's Degree in Electrical Engineering from IITMadras in India, and a Master's Degree in Computational Science and Engineering from the University of California, SantaBarbara.
Janick Bergeron is a Fellow at Synopsys Inc. responsible for the development and specification of the functional verification methodology to be supported by their digital simulation products. He is the author of the best-selling Verification Methodology Manual for SystemVerilog and of the Writing Testbenches book series. Both are the first industry references on modern functional verification techniques and methodologies.
Mr. Bergeron holds a Bachelors Degree in Engineering from the Universite du Quebec a Chicoutimi, a Master of Applied Sciences in Electrical Engineering from the University of Waterloo VLSI program, and an MBA from the University of Oregon through the Oregon Executive MBA program.
Yoshio Inoue is Chief Engineer of Design Technology Div. at Renesas Technology Corp., which was formed through the merger of semiconductor operations of Hitachi and Mitsubishi on April 1st, 2003.
He holds a Bachelor of Science Degree at Tokyo Denki University. He joined Mitsubishi Electric as a gate array design engineer in 1984. Since 1989 he has been involved in advanced EDA design methodology development and EDA design systems to support the US's high-speed, high-complexity SoC designs.
When Renesas was formed, he focused more on RTL prototyping technology for Japanese and US customers designs. He has expanded his area of focus to ultra low power design methodology such as application processors for cellular phones and is a pioneer in the area of hierarchical power management.
David Flynn, a Fellow in R&D at ARM Ltd., has been with the company since 1991, specializing in System-on-Chip IP deployment and methodology. He is the original architect behind ARM s synthesizable CPU family and the AMBA on-chip interconnect standard. His current research focus is low-power system-level design. He holds a number of patents in on-chip buses, low -power and embedded processing sub-system design and holds a Bachelr of Science Degree in Computer Science from Hatfield Polytechnic, UK and a Doctorate in Electronic Engineering from Loughborough University, UK. He is currently Visiting Professor with the Electronics and Computer Science Department at Southampton University, UK.