Customer Reviews

Verification Methodology Manual for SystemVerilog

5 star:		(2)
4 star:		(2)
3 star:		(1)
2 star:		(0)
1 star:		(0)

 

 

I consider this book to be a good VMM Reference.

Please don't mistake this to be a complete SystemVerilog Bible. This is Verification Methodology Manual (VMM), and after reading this book, it's not a bad idea to think if this methodology is the right one for your project.

This book outlines several "rules", "recommendations", "suggestions" and "alternatives" in using VMM for your project. I found these to be useful to a certain extent. Although the examples weren't quite informative. For starters I would also suggest reading general book on object oriented programming along with this book.


************* BUYING THIS BOOK? READ THIS: ***************

Before you buy this book, check if you/your office has Synopsys VCS installed (Along with Documentation). If you happen to have complete VCS installed, you would get this book (pdf version) for FREE along with the VCS documentation. I came to know about this after buying this book. Any ways, it is good to have a hard copy.

Also, I found it useful to have other SystemVerilog books along with this one. It makes life easy to understand a (new) language and (new) methodology.

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The book starts off fairly well through the first three chapters. Then all of a sudden it makes a huge leap and it becomes very difficult to follow. There are a lot of very advanced topics that require a lot of object oriented programming experience to understand. On my second reading I saw that even Janick says that he does not expect you to understand VMM on the first reading.

A class based methodology is a complex topic and the VMM book does not do much to make it any easier. If you are a C++ (or something similar) guru, then you might enjoy this book. Otherwise, save your money and download the white papers from the web.

This is a very good book. However, as a newcomer to VMM, I initially got more out of "A Pragmatic Approach to VMM Adoption" by Cohen, Venkataramanan and Kumari. I use both books extensively. Since reading "A Pragmatic Approach", Bergeron's book is much more understandable and useful.

I got this book at work to learn about VMM and the use of it.
It covers high level concepts and recommendations on developing a successful verification environment. It does not teach you the syntax or the basics of System Verilog. Beside teaching you these high level concepts, it covers in detail the use of the VMM base classes offered with Synopsys' VCS tools.
The book has code example in each topic covered which will make it easier to understand.
The topics covered include, but not limited to, Verification planning, assertions, testbench infrastructure, stimulus/response and coverage.
If you are using VMM in your development, then this book is definitely the manual that goes with it.
A must have for a successful verification engineer working with VMM. (6 out of 5 stars)

I have not gone through the entire thing, but this is good for some one who knows verilog, and understands Verification.