Customer Reviews

The Verilog® Hardware Description Language

5 star:		(4)
4 star:		(3)
3 star:		(0)
2 star:		(2)
1 star:		(3)

 

 

This book should be used only by the experienced users that can filter out problematic sections.
Major problems:
- first chapter, "recommended" by authors for university courses, is extremely chaotic (begin..end blocks are called loops, exercises ask you to use loops before introducing them, etc.)
- cover of the latest edition claims coverage of the latest Verilog standard - unfortunately it is very poor coverage: new interesting features such as libraries and configurations are not mentioned at all!
- I had to work hard during many trainings to correct bad coding styles showing in students reading this book as their first Verilog publication
- the book is grossly overpriced...

Main advantage:
- good set of examples

This book takes the beginning verilog student through a quick tutorial with exercises for practice as you learn. The book is well written for learning the subjects it presents. The only reason it does not get five stars is because it is not a good reference. The information is in there, however, the index is incomplete and the information is scattered throughout the book. Finding information takes some manual searching. Otherwise, it is one of the best books for learning verilog. I used the included software instead of the Xilinx Foundation Series software for Students. The included software supports the complete verilog set, not just the sythesizable subset. If you are experienced, looking for a good reference , will spend nearly $150 for a book, and do not need a verilog simulator, I recommend the Complete Verilog Book. See my review of that book for more information.

'The Verilog Hardware Description Language' is a very good tutorial and reference for intermediate designers.

I used this book in an upper level hardware design course. The course had a beginning Verilog course as a prerequisite. I hadn't taken that course but I had experience in digital design and VHDL. This book got me up to speed quickly with it's many examples and tight explanations of the Verilog Language.

Some pluses:

-Example designs are short, complete, and simulatable. Most are even synthesizable. This is good because an example can be quickly understood in its entirety. You don't need to flip through and stare and multiple pages to get an idea of what's going on. If you insist on having them, there are two long, practical examples towards the end of the book.

-The text is very well written. Similar in style to 'The C Programming Language by Kernighan and Ritchie.'

-Verilog 2001: Focuses on 2001, which is a little clearer than previous standards. I think all tools support 2001 by default now so that should be used.

Some minuses:

-Too expensive.

-Not enough discussion on how Verilog constructs are compiled and netlisted. This is critically important in FPGA/ASIC design. However, this book is not any worse than other HDL books in this respect. It's just so important, I really haven't seen anything that gives the topic the treatment it deserves.

Possible minus:

-Not really for beginners. This is not a hardware design text.

I haven't used the CD that came with the book so I can't comment on that. My guess is anything on that CD is not as good as industry standard tools like Mentor's ModelSim.

Overall a very impressive book that will get you to productivity quickly in a Verilog project.

I thought this book was great. It covers the verilog language in a way that makes it clear exactly how the simulator works, so you can predict the results of your program with confidence. This book is also very clear as to what hardware will be generated by what constructs. The very important difference between latches and flip-flops is fully covered here, as is a full description of which constructs will generate (probably unwanted) latches. This was my third Verilog book, and this was the only one that left me feeling confident as to the extent of my knowledge. This is the only one you need.

The only shortcoming of this book is that the authors decided not to cover every llittle bit of verilog, which would have removed the need to consult the standard. Since the standard is so unreadable, I think that this was a crying shame, but I don't think that this will pose a real problem for most readers. Besides, I haven't seen a credible alternative.

It's somewhat rare to find an engineering text that manages to
be both readable and informative. The Verilog Hardware
Description Language, by Donald E. Thomas and Philip R. Moorby,
fulfills both of these aspects.

The book is divided into four sections, any of which would be an
excellent reference alone.

The first section is a tutorial introduction comprised of one
chapter. This concise introduction conveys the basics of the
language and explains digital hardware modelling.

More advanced topics, essential for any ASIC designer or graduate
student are covered in the next section. Some of the topics are
behavioral modeling, concurrent processes and switch level
modeling. Despite the more complex nature of the chapters in this
section the text still maintains the high level of readability
in the introductory section.

The final two sections are three large examples and a reference
to the Verilog hardware description language.

I would recommend this book to any graduate student interested in
learning Verilog or VHDL users interested in becoming skilled in
Verilog.

Before buying this book, make sure you don't buy this book because it has a Synthesis and Simulation tool with the CDROM.

2 important notes: - Veriwell simulation tool can work not "very well". - Synplicity will no longer give out free trial liciencse for its synthesis tool.

The book is not well written and not suitable for a beginner to read. But it does have some good examples in the book. However, I don't think it is worth to pay $98 for such book.

thomas was one of my prof's, but still this book needs some work from a programmers perspective. there were few hard to understand examples and no clear progression through the book. good bedtime reading

Was sharing this book with my workmate. Found it pretty useful. I think its a great reference book to have.
It has
+ A great Index.
+ Good examples.
+ Been written by the masters of Verilog.
- A lot of words (ie some people might find it very 'wordy')

Every ASIC/FPGA designer I know has this one in there shelf. So go for it.

I really liked the book since I had read a copy from my school library hence I decided to purchase one. Unfortunately since Amazon doesn't set any standards that all sellers should meet, my purchase was a rip off.

I order the book assuming it was a North American Copy Unfortunately The one that I received was printed in CHINA & FULL OF GRAMMATICAL MISTAKES please watch out for the seller "Express_Textbook" do not purchase unless u want a Chinese Version.

The seller does not specify this information so once you have made a transaction you'd have to go through the hassle of returning it.

A NOTE TO AMAZON ADMIN: PLEASE INSIST SELLERS WHEN SELLING NEW PRODUCTS TO SPECIFY DETAILS SO THAT CUSTOMERS CAN MAKE THE RIGHT CHOICE.

The claim that this book has become the standard for learning Verilog is true.
I use Verilog a lot but I still wish I had read this book before writing Verilog codes.