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16 Reviews
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11 of 11 people found the following review helpful:
5.0 out of 5 stars
A Necessary Text,
By j.wetstein@ieee.org (Maryland, USA) - See all my reviews
This review is from: Verilog Designer's Library (Paperback)
I am a senior systems engineer. This book has been instrumental in getting some of our new engineers quickly up to speed in Verilog so that they could begin doing design right away. This book doesn't try to solve every problem because it doesn't have to - instead it enables the reader to learn the cornerstones of design, teaching the user necessary skills and not simply cookbook repetitions. Synthesizable code is treated more fairly in this text than others. I was very pleased to add this to my library.
13 of 15 people found the following review helpful:
5.0 out of 5 stars
A good library of models,
By
This review is from: Verilog Designer's Library (Paperback)
I was looking for models for a dual-port RAM and a FIFO. I couldn't find any book that had examples of either one of them. This book does and in great detail. That was worth the price of the book for me.
5 of 5 people found the following review helpful:
4.0 out of 5 stars
Some Good Points,
By Cliff The Engineer (Fremont, CA USA) - See all my reviews
This review is from: Verilog Designer's Library (Paperback)
This book is good for beginners, it has a few good ideas in it. The Behavioral vs. RTL versions of the code is pretty useless, but the RTL vs. Simulation versions are useful. Getting a quick and dirty unit test bench up and running is a good idea. But DO NOT USE THE ASYNCHRONOUS FIFO. It does not work. If you are crossing clock boundaries, this is not the way to do it!
10 of 12 people found the following review helpful:
1.0 out of 5 stars
value/price=almost zero,
By "_chm_" (Kanata, ON, Canada) - See all my reviews
This review is from: Verilog Designer's Library (Paperback)
This is a bad book, overall. I just pick 3 exemplary issues:.) The distinction between behavioural and RTL code in the examples is only there to double the number of pages. The listings are essentially the same, they differ in typically, like, 5 lines. Moreover, most synthesis tools would accept both programs and create the same circuit. .) creating Verilog code from 3 pages of C which could be done in 10 lines of Perl is not really state of the art. .) Worst of all: The asynchronous fifo does not protect the pointers on the clock domain boundary, so it is unusable in the real world. Either Bob Zeidman is not really up to date with his Verilog design skills, or it's the Dogbert priciple of "Beware the advice of successful people; they do not seek company."
4 of 4 people found the following review helpful:
5.0 out of 5 stars
Best Verilog Book I've seen,
By
This review is from: Verilog Designer's Library (Paperback)
With many verilog books out there, this one has to be the best I've seen. It has real world modules, and explains what went into each module. This book is a MUST for any Beginner->Advanced ASIC designer. Highly recommended!!
15 of 20 people found the following review helpful:
2.0 out of 5 stars
Should be renamed to "Verilog Beginner's Library",
By Yitzak Shamir (San Jose, CA) - See all my reviews
This review is from: Verilog Designer's Library (Paperback)
I am a power user of Verilog. I have "all" the books on Verilog. I bought this book just to make sure that my library is complete. Atleast 1/3rd of this book is complete waste. Who writes behavioral code for counters and adders? Behavioral code section for all the modules is unnecessary. Author should remove them and save paper (save trees too). Behavioral code is used in real life to simulate parts of design which can not be described in RTL like memories or some processor macros and not to describe simple designs. A real life designer will never keep such simple models in his library. Most models are suitable as a starting guide for a beginner. I think book should be renamed as "Verilog Beginner's Library" BTW I will surely congratulate author for collecting many different kinds of models in one place. I give 2 stars for this effort.
2 of 2 people found the following review helpful:
5.0 out of 5 stars
A good handbook to start to build your project,
A Kid's Review
This review is from: Verilog Designer's Library (Paperback)
I helped a design engineer in my group to start a CRC RTL coding in our project by using the code from this book as a basis and found the book is very useful. There are three RTL coding techniques mentioned in this book: reliability, scalability and portability. I think they are important and not mentioned in the books I have read.I want to submit this comment but I could not get rid off the age which can only allow me to put max 12? please remove the age from the comment and you should modify this part from your web site.
2 of 2 people found the following review helpful:
5.0 out of 5 stars
An indispensable starting point,
By A Customer
This review is from: Verilog Designer's Library (Paperback)
Tired of reinventing the wheel? Complete designs are provided for basic building blocks such as FIFOs, RAM controller, dual port RAM, State machines, etc. This book has proven an indispensable starting point.
1 of 1 people found the following review helpful:
4.0 out of 5 stars
This book and examples were very useful in improving my Verilog skills,
By
This review is from: Verilog Designer's Library (Paperback)
This book was the ideal book for my needs. I found the explanations and code examples to be complete for writing Verilog. I have used as an ongoing reference over several years and many employment positions.
1 of 1 people found the following review helpful:
5.0 out of 5 stars
Excellent book on verilog,
A Kid's Review
This review is from: Verilog Designer's Library (Paperback)
Bob's "Verilog Designer's Library" is an excellent book for verilog programmers. It does help me much. Every example in this book is very practical to engineers. I like it. |
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Verilog Designer's Library by Bob Zeidman (Paperback - June 25, 1999)
$95.00 $69.99
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