Customer Reviews

Verilog HDL: Digital Design and Modeling

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This book is full of examples, completely worked out. That's valuable. However, I wanted to point out what you won't find in this book, so that you'll look elsewhere if you need it. As I should have.

Most important: There is NO discussion of synthesis at all. None. You will not learn from this book which Verilog constructs are synthesizable, or how they are synthesized. You may very well get the impression from this book that everything you do in Verilog can be made into hardware, because the book never says otherwise. In fact, take a hint from the subtitle of this book: it contains the word "modeling" and does not contain the word "synthesis". You will not learn, for example, that the reg type does not necessarily synthesize into a register - which is key knowledge if you want to use combinatorial logic in a always block and are worried that needing to use a reg type means it will be clocked. I had to look to the web to discover this.

Next: Book is copyrighted 2007 but as far as it is concerned Verilog-2001 doesn't exist. Verilog-2001 has a lot of nice syntax and feature improvements. No reason to be limited to earlier Verilog syntax/semantics any more, but you won't learn anything about it here. (It would have made the examples shorter too.)

Finally: There is no discussion of the Verilog "gotchas", as described with terrific explanations in the papers by Sutherland, Mills, and Spear. (Google for "Standard Gotchas Verilog" and "More Gotchas Verilog".) It would really be nice in this textbook to have coverage of the several of these common issues, especially sign-extension (or non-extension) when connecting or operating with nets/regs of different sizes, and also the issues of case fullness or parallelness. (The papers came out contemporary with the book, I'm not suggesting that the author should have copied the papers here, but surely he knew of these issues independently and could have covered them.)

Anyway - books in the HDL field (or maybe just Verilog) seem to be poor in general, for a variety of reasons. This one isn't badly written, it just doesn't cover some important stuff. And in particular, it doesn't cover synthesis (esp. in the FPGA context), which is what I was looking for.

Oh, one more thing. 70 pages are devoted to "gate level modeling". Wow. There must be some reason to have that stuff in the language; it must be useful to someone. But I sure don't know why anyone needs to use it, especially not the beginning students that this book is aimed at. And the same for K-maps. K-maps have a long history and they're very useful if you're optimizing gates by hand. But now we have logic compilers (i.e., Verilog/VHDL compilers) and I can't see any reason why you can't just go from state machine diagrams to synthesizable code without ever touching a K-map. Looking at the diagrams in this book you'd think they were crucial. Very odd.

I've been a fan or Mr. Cavanagh books beginning with his book "Digital Computer Arithmetic". Digital Computer Arithmetic: Design and Implementation (Computer Science) which I applied to an IC design I was working on (Philips 8051 derivative circa 1990). Now, I've found that I need to update my design skills and have a need to learn and apply the Verilog HDL language to apply to SDR radio design project ideas. This book fits that need. The book is not intended to be a tutorial on logic design. It is intended to be a tutorial on the complete Verilog language together with wide variety of design examples. The book begins with an overview of the Verilog language structure, language elements, and modeling concepts. Next the Verilog language elements, expressions, are covered followed by in-depth discussions of gate-level, dataflow, and behavioral, structural modeling. User-defined primitives, tasks, and functions are given apt attention. The book closes with addition design examples (a simple RISC CPU), and event queues. Note that the author uses the SILOS simulator for all examples. I found this to be an issue due to the cost of SILOS. However, a after a little research ending up with a quick trip to Wikipedia uncovered a nice low-cost Verilog design environment called LogicSim by Zeemz ([...]). Although I don't endorse any particular product, I've had no issues with LogicSim working my way thorough various portions of this book. I've also found that having a FPGA design kit (in my case a Xilinx Spartin-3 kit) is quite useful to apply the concepts. Your mileage may vary.

Note that if you are new to Verilog (but not to programming in general) the book is quite easy to read. Note that in order to fully grasp Verilog, in my opinion, you need to read the entire text (all 770+ pages) and work the examples. The explanation of Verilog is not condensed with follow-on project. The approach is to get you started with simple examples of what is presented in latter chapters. The various parts of Verilog are then covered in more depth. Some may not like this approach opting, instead, for a book that has complete projects on a specific kit (Xilinx Spartan 3, etc.). This is not the book for those individuals. There are plenty of books on Verilog. This book happens to fit my need to cover Verilog with, what I would describe, and "architectural twist". Mr. Cavanagh's other book complements this book.

The contents of the book are as follows:

Chapter 1 Introduction
Chapter 2 Overview
Chapter 3 Language Elements
Chapter 4 Expressions
Chapter 5 Gate-Level Modeling
Chapter 6 User-Defined Primitives
Chapter 7 Dataflow Modeling
Chapter 8 Behavioral Modeling
Chapter 9 Structural Modeling
Chapter 10 Tasks and Functions
Chapter 11 Additional Design Examples
Appendix A Event Queue
Appendix B Verilog Project Procedure
Appendix C Answers to Select Problems

Clearly one of the best books written on Verilog HDL. It covers the complete Verilog language in detail, including language elements and expressions. Chapters include comprehensive coverage of built-in primitives, user-defined primitives, dataflow modeling, behavioral modeling, and structural modeling, all with numerous examples that illustrate the design principles of each modeling method. There are excellent examples on the Hamming code, the Booth algorithm, and a pipelined RISC processor, all completely designed using Verilog.

The Verilog simulator used in the book is the SILOS simulation environment from Silvaco Intenational. Design examples in the book include the design module, the test bench module, the outputs, and the waveforms. The design topics also include the associated theory.

No book will tell you how to design your particular Verilog project; however, using the principles and practices outlined in this book and your own innate ability you can accomplish anything. An excellent book for both academia and industry.

The Author of this book gives indepth knowledge of Verilog and provides a very good start to the beginner. Sticks to almost single development environment which is widely used. I am still in process of reading this book.

Another great book by the author. Extremely well-written, covering the language elements and expressions. Also, the various modeling constructs of built-in primitives, user-defined primitives, dataflow modeling, behavioral modeling, and structural modeling are presented in detail. The book has numerous design examples for all of the modeling constructs. These include combinational logic and sequential logic for finite-state machines, both synchronous and asynchronous for Moore and Mealy machines. There are also counters, shifters, and arithmetic designs of high-speed adders/subtractors and multipliers, all designed in Verilog. The theory for the designs is presented first, followed by the Verilog designs. The Verilog design of a RISC processor is also included as well as answers to many of the problems located at the end of each chapter. An excellent book that is highly recommended.

One of the best books on Verilog. Comprehensive and extremely well written. All modeling constructs are covered: built-in primitives, user-defined primitives, dataflow modeling, behavioral modeling, and structural modeling, all with numerous design examples. These include: counters of different moduli, shift registers, Hamming code error detection and correction, Booth algorithm, and Moore and Mealy finite-state machines.

The designs also include iterative networks and a pipelined RISC processor. Each design example in the book includes the design module, the test bench module, the outputs, and the waveforms. Most other books do not include outputs and waveforms to verify the correct operation of the design.

I have been a hardware designer for several years and find both the text and the Verilog code very easy to read. A great book to have on your bookshelf. Highly recommended.

Well written and comprehensive. Numerous design examples, for all modeling constructs. There is even the complete design of pipelined RISC processor, plus additional logic functions: counters, shifters, Hamming code, Booth algorithm, Moore and Mealy machines, plus much more. The author includes the design module, test bench module, outputs, and waveforms for each design -- something that other books do not include. As a logic designer for many years, I highly recommend this book.

I have several books on Verilog, but this is by far the best book. Well written and very easy to follow. There are numerous design examples using all of the modeling constructs: dataflow, behavioral, and structural. Also chapters on built-in primitives and user-designed primitives. I learned a great deal from the author's book on how to design both combinational and sequential logic using Verilog. I especially like the design of a pipelined RISC processor. Recommended. Well worth it.

The book provides a firm foundation from which to learn Verilog. Each chapter presents many Verilog design examples, which include carry lookahead adders, code converters, counters of various moduli, plus the theory and design of Moore and Mealy synchronous and asynchronous sequential machines. Also included is the theory of the Hamming code and the Booth multiplication algorithm, both designed using Verilog. There is an excellent Verilog design of a small pipelined RISC processor. The author also discusses tasks and functions and provides examples of these in Verilog. The book is comprehensive; the designs include the Verilog code, the test bench, the outputs, and the waveforms using the SILOS Simulation Environment software.

I am a graduate student in Computer Engineering taking a course in Verilog. We have ten labs to do: combinational logic, sequential logic, adders, counters, multipliers, ALUs, etc. This book has helped considerably by describing the theory, concepts, and procedures to be used when designing the labs using Verilog. It is a great book to augment the lectures. Well written and easy to understand.