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Explains the language through simple examples.
Explains the syntax of language using commonly-used design terminology.
Explains the behavioral style, the dataflow style, and structural style in detail.
Concepts of delay and timing are clearly explained.
Testbench writing is made easier by providing a number of examples.
Many hardware modeling examples have also been provided to make this an excellent reference.
"An excellent reference book that shows many modeling examples"
Learn Verilog HDL the fast and easy way. Use this primer for a thorough understanding of the basic building blocks of Verilog HDL.
Find out how to model hardware and test it using the various constructs provided by Verilog HDL.
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Most Helpful Customer Reviews
15 of 16 people found the following review helpful:
5.0 out of 5 stars
An excellent introduction and reference,
By A Customer
This review is from: A Verilog HDL Primer, Second Edition (Hardcover)
This is a very good introduction to Verilog coding. I read the book prior to taking a formal Verilog class, and walked into the class very well prepared. The book is well organized, and the index is very complete, which is good for newbies (like myself) who still need a syntax and usage reference.
12 of 13 people found the following review helpful:
2.0 out of 5 stars
Regurgitation of LRM,
By A Customer
This review is from: A Verilog HDL Primer, Second Edition (Hardcover)
This book is basically a regurgitation of the language reference manual and really does not give the reader any insight into when and how to use particular language constructs. For example on page 148 the author discusses module ports and has an example of a port redeclaration, but he neglects to discuss why you would wish to redeclare a port as a wire. If you are learning Verilog because you are going to use it in an actual design look elsewhere.
4 of 4 people found the following review helpful:
3.0 out of 5 stars
A little disappointed,
By
Amazon Verified Purchase(What's this?)
This review is from: A Verilog HDL Primer, Second Edition (Hardcover)
With such a high rating, I had hoped for something better.
If you are looking for a very introductory lesson on the workings of Verilog, this is for you. However if you are looking for something that will help you learn to write complex code, this is not it. My biggest complaint is that this book needs to be hit pretty hard by an editor who actually understands Verilog enough to find the syntax errors and omissions in the example code. If this is supposed to be a "primer" all of the examples should be technically and syntactically correct, and they are not. I am able to find mistakes and this is my first foray into Verilog. Also note: this does not teach anything about synthesizable code. That's another book, but the difference is never even mentioned. Almost everything in this book will help you learn how to write test benches for you synthesizable modules.
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