Customer Reviews

A Verilog HDL Primer, Second Edition

5 star:		(3)
4 star:		(1)
3 star:		(2)
2 star:		(1)
1 star:		(0)

 

 

This is a very good introduction to Verilog coding. I read the book prior to taking a formal Verilog class, and walked into the class very well prepared. The book is well organized, and the index is very complete, which is good for newbies (like myself) who still need a syntax and usage reference.

This book is basically a regurgitation of the language reference manual and really does not give the reader any insight into when and how to use particular language constructs. For example on page 148 the author discusses module ports and has an example of a port redeclaration, but he neglects to discuss why you would wish to redeclare a port as a wire. If you are learning Verilog because you are going to use it in an actual design look elsewhere.

With such a high rating, I had hoped for something better.

If you are looking for a very introductory lesson on the workings of Verilog, this is for you. However if you are looking for something that will help you learn to write complex code, this is not it.

My biggest complaint is that this book needs to be hit pretty hard by an editor who actually understands Verilog enough to find the syntax errors and omissions in the example code. If this is supposed to be a "primer" all of the examples should be technically and syntactically correct, and they are not. I am able to find mistakes and this is my first foray into Verilog.

Also note: this does not teach anything about synthesizable code. That's another book, but the difference is never even mentioned. Almost everything in this book will help you learn how to write test benches for you synthesizable modules.

While some might say that it's a beginners' book, you will
end up using this book the most. I have several Verilog
books in my cube at my work, but this is the book my
colleagues come very often to look up. This has excellent
and authentic descriptions of all Verilog language rules
and primitives. It also explains how and when to use
different Verilog constructs. I bet you will not regret
having this book.

Occasionally you see books that seem to be compiled by the author's lecture notes, this is one of them. It would still be ok if the notes were good, however this one isn't. It does it's job presenting the basics of Verilog, but on harder to understand concepts such as blocking/non-blocking procedural assignments and procedural continuous assignment, the author does an aweful job explaining it, which is where it counts the most. Similar problems appear throughout the book, and I can never understand why it has attained a four star rating, which is when I purchased it. If you can find a better book, go for it!

This book is well organized.All the chapters are thoroughly written and hence easily understood by a beginner.I would personally refer this book both for a beginner and a practicing engineer.

That's the way to describe it. The matter is not very verbose. It is comp[avt & the book moves fast. This is achieved, unfortunately, at the expense of a sufficient number of complete, working examples, which makes this book slightly unsiited for the semi-competent but the competent will be pleased with the fast pace at which concepts are introduced.