A Verilog HDL Primer, Third Edition [Hardcover]

J. Bhasker (Author)

Book Description

Publication Date: January 2005

- Written for new users. - Explains the language through simple examples. - Explains the syntax of language using commonly-used design terminology. - Explains the behavioral style, the dataflow style, and structural style in detail. - Concepts of delay and timing are clearly explained. - Testbench writing is made easier by providing a number of examples. - Many hardware modeling examples have also been provided to make this an excellent reference.

Also includes exercises for every chapter and expanded coverage of more language features including test bench writing strategies.

Third edition is based on IEEE Verilog 2001 Standard. It includes explanations of all the new features introduced in this version of the language, with examples.

Editorial Reviews

Review

" I would recommend as text for a course as part of Electrical Engineering curriculum" -- Lincoln A. McLoud, Bell Labs

"I have found the book easy to read, and an excellent reference" -- Sharad Seth, University of Nebraska at Lincoln

"This text is a definitive learning resource and an excellent reference for the experienced designer." -- Vincent Zeyak Jr., Agere Systems

From the Back Cover

With this book, you can:

- Learn Verilog HDL the fast and easy way. - Obtain a thorough understanding of the basic building blocks of Verilog HDL. - Find out how to model hardware. - Find out how to test the hardware model using a test bench.

"This text is a definitive learning resource for the student of Verilog as well as an excellent reference for the experienced designer. The features of Verilog are clearly covered with both explanations and examples. Especially beneficial is Appendix A which contains a syntax reference in alphabetical order" - Vincent Zeyak Jr., Agere Systems

"I have found the book easy to read, to the point, and an excellent reference" - Sharad Seth, University of Nebraska at Lincoln

See all Editorial Reviews

Product Details

• Hardcover: 400 pages
• Publisher: Star Galaxy Publishing; 3rd edition (January 2005)
• Language: English
• ISBN-10: 0965039161
• ISBN-13: 978-0965039161
• Product Dimensions: 9.2 x 7.2 x 1 inches
• Shipping Weight: 1.6 pounds (View shipping rates and policies)
• Average Customer Review: 4.2 out of 5 stars  See all reviews (5 customer reviews)
• Amazon Best Sellers Rank: #999,776 in Books (See Top 100 in Books)

Customer Reviews

Most Helpful Customer Reviews

11 of 14 people found the following review helpful:

5.0 out of 5 stars Excellent Book on Verilog, January 2, 2008

By 

Michael Andrews "Engineering is FUN! ... usually" (Lynnwood, WA) - See all my reviews
(REAL NAME)   

This review is from: A Verilog HDL Primer, Third Edition (Hardcover)

Very impressive book. Well written, the sections 'flow' nicely, thoroughly covers Verilog, and includes examples with clear explanations. Excellent index. I have about 6 years of design experience in VHDL and 18 years of embedded C development, 34 years in Engineering, so picking up Verilog went quickly.

I give a lot of credit to this book for keeping clear the big and small 'pictures' of what makes up Verilog. Highly recommend it to both new and 'seasoned' (I refuse to say 'old' :-) ) HDL designers. Great addition to your Engineering library. But unlike many books in most Engineering libraries, you'll actually use this one. :-)

6 of 7 people found the following review helpful:

5.0 out of 5 stars Great Verilog book for Beginners, April 22, 2008

By 

Joseph J. Pedalino - See all my reviews
(REAL NAME)   

This review is from: A Verilog HDL Primer, Third Edition (Hardcover)

This book is well organized from beginning to end and the index is excellent for finding what you need. I found that the examples are complete and relevant to what you need to get started with Verilog. Each chapter explains the subject matter with enough examples so that the reader can understand the subject. Compiler directives are covered well enough for the beginner to use the commands. Memories were covered in sufficient detail so that I could create a RAM for my lab class. Even the $readmemh and $readmemb directives were covered. I enjoyed reading the book because it is well laid out complete. I think that the beginning student will like and enjoy using this book.

1 of 1 people found the following review helpful:

1.0 out of 5 stars at BEST a mediocre book, March 20, 2011

By 

carol49 - See all my reviews

Amazon Verified Purchase

This review is from: A Verilog HDL Primer, Third Edition (Hardcover)

This book should only be used because Palnitkar's book is going out of print. The author dwells on material that is useless. For example, he spends an entire chapter on UDPs---something you can't even synthesize.

In fact, a MAJOR flaw in the book is the author completely ignores synthesizability. Readers should understand that certain syntax in Verilog is not synthesizeable---i.e., design automation tools won't convert it into a circuit or FPGA implementation---and therefore the syntax is utterly useless. Moreover, certain syntax is preferred because it leads to more efficient synthesized designs.

The author ignores all of that, which makes the book essentially worthless for practicing engineers.

The author spends pages on switch-level designs. I am unaware of anyone who uses switch-level descriptions. Switch-level is useless for FPGA designs. The author should replace all of the switch-level pages with pages on synthesizability.

Finally, the author has the irritating habit of declaring nets with bit '0' as the most significant bit sometimes and other times bit '0' is the least significant bit. Pick one convention and stick with it.

Overall I would NOT recommend this book if you are an engineer out in industry. Try and get a copy of Palnitkar's book. You will be far, far better off.