Customer Reviews

A Verilog HDL Primer, Third Edition

5 star:		(4)
4 star:		(0)
3 star:		(0)
2 star:		(0)
1 star:		(1)

 

 

Very impressive book. Well written, the sections 'flow' nicely, thoroughly covers Verilog, and includes examples with clear explanations. Excellent index. I have about 6 years of design experience in VHDL and 18 years of embedded C development, 34 years in Engineering, so picking up Verilog went quickly.

I give a lot of credit to this book for keeping clear the big and small 'pictures' of what makes up Verilog. Highly recommend it to both new and 'seasoned' (I refuse to say 'old' :-) ) HDL designers. Great addition to your Engineering library. But unlike many books in most Engineering libraries, you'll actually use this one. :-)

This book is well organized from beginning to end and the index is excellent for finding what you need. I found that the examples are complete and relevant to what you need to get started with Verilog. Each chapter explains the subject matter with enough examples so that the reader can understand the subject. Compiler directives are covered well enough for the beginner to use the commands. Memories were covered in sufficient detail so that I could create a RAM for my lab class. Even the $readmemh and $readmemb directives were covered. I enjoyed reading the book because it is well laid out complete. I think that the beginning student will like and enjoy using this book.

This book should only be used because Palnitkar's book is going out of print. The author dwells on material that is useless. For example, he spends an entire chapter on UDPs---something you can't even synthesize.

In fact, a MAJOR flaw in the book is the author completely ignores synthesizability. Readers should understand that certain syntax in Verilog is not synthesizeable---i.e., design automation tools won't convert it into a circuit or FPGA implementation---and therefore the syntax is utterly useless. Moreover, certain syntax is preferred because it leads to more efficient synthesized designs.

The author ignores all of that, which makes the book essentially worthless for practicing engineers.

The author spends pages on switch-level designs. I am unaware of anyone who uses switch-level descriptions. Switch-level is useless for FPGA designs. The author should replace all of the switch-level pages with pages on synthesizability.

Finally, the author has the irritating habit of declaring nets with bit '0' as the most significant bit sometimes and other times bit '0' is the least significant bit. Pick one convention and stick with it.

Overall I would NOT recommend this book if you are an engineer out in industry. Try and get a copy of Palnitkar's book. You will be far, far better off.

I'm a hardware design engineer who works mostly with FPGAs/CPLDs and this is my go-to Verilog reference. It's got extensive coverage of Verilog 2001's features, something which most books written before 2002 or so will be missing.

Bhasker explains the syntax of every feature of Verilog-2001, including both synthesizable and non-synthesizable constructs. It's true that he mixes them together in the book, and also that he doesn't spend much time explaining which things will and won't synthesize. I don't think that's a problem though, considering that what will or won't synthesize changes from tool to tool.

To my knowledge there is no formalized Verilog subset for synthesis. While it's true that delays aren't synthesizable today, who's to say they won't be at some point in the future? I think that discussions of what is and isn't synthesizable are best handled in your synthesizer's documentation.

My one and only complaint about this book is that the page numbers in the table of contents and the index are off by a few pages, so they must be treated as "guidelines" for where in the book your desired information actually resides. This is pretty annoying but the book is still worth 5 stars for its content.

Hi,

Great book.

Very good introduction to the newer releases of Verilog, includes useful code examples. Clearly explains what is synthesizable and what is not.

Dan