Customer Reviews

Verilog HDL

5 star:		(6)
4 star:		(12)
3 star:		(3)
2 star:		(4)
1 star:		(3)

 

 

This book starts from very basic knowledge of Verilog. It assumes no prior knowledge of the language. It starts from explaining the different data types of Verilog with very clear examples. Then it shows you how to create a module and why is it important to divide your design into several modules. Then it teaches you how to create a circuit at gate level modeling. The schematics of the the code is given in the book, so you can clearly see the relationship between the schematics and its corresponding Verilog code. Then it moves to data flow modeling, again with very clear examples. After that, it moves to Behavioral Modeling. This the only book that gives me a very good understanding of always block, initial block, reg data type, and most importantly blocking and non blocking assignment. It has excellent example of how to create a state machine. The rest of the book teach you some tips that will make it easier for you to write your code. It also has some very good examples of how to create a testbench. Almost every example has its own testbench. So, you will learn how to create a testbench as you read the book from the very beginning. I only have 2 complains of the book. One is it doesn't tell you which part of the language is synthesizable until near the end of the book. Second is it doesn't tell you which part of the examples is the new features in Verilog 2001. This could be problematic if your simulator and synthesis tool does not fully support Verilog 2001. But other than that, I am fully satisfied. When I first learned Verilog, I browsed many other books. And this one is absolutely the best one. Without this book, I won't be able to finish my projects ahead of time with an A+. Good job Mr. Palnitkar!

This book is suitable for its time, but the contents are more intended for Verilog models. It talks a lot about the Verilog syntax; however, the title mislead me - VERY LITTLE discussion about Verilog for Synthesis. There is only one chapter devoted to systhesis, and this chapter happens to be the LAST chapter of the book.

Don't get me wrong. This is a good book for beginners in Verilog HDL. It is a "MIX-BAG" of syntax only for understanding (NOT synthesis). After reading this book, one should be familiar with the application of Verilog for Simulation and Modeling, but one may still have to get a synthesis book or training to further utilize the power of Verilog for FPGA or ASIC design (I am an FPGA designer). I gave it 3 stars due a misleading title and the fact that only a single chapter was devoted to synthesis topic.

One topic bothers me. Why would someone use Verilog HDL to model the Transisor Level (he calls it the switch level)? Isn't this the reason SPICE programs were designed to do? Besides that, Verilog HDL is still YET to add ANALOG capabilities.

The early chapters are an excellent guide to the syntax and wiring connections, they clearly outline potential pitfalls. Chapters 5 & 6 cover designs from too low a level. I'm sure other real-world designers will agree that modeling a flip-flop with gates just flops. I'm on Ch. 7 now and except for a reference on (min:typ:max) back to (yech!) chapter 5 the author finally gets back to real world design and synthesis (though he doesn't differentiate). Design for synthesis is a different animal than test design and where they diverge should be hi-lighted. But the explanations are clear and eventually the important levels of verilog design are covered. So if read thoughtfully it is a very good intro to verilog, but beware the useless filler.

This is perhaps the best book to Verilog for those who are new to the language. There are certain aspects of the book that are very applicable to real life situations (chapter 2). It is a very well written book! Yes it is sometimes very basic, but it is intended to be that way. If you are looking for an advanced book, this is not the book for you. But if you are looking for a very good foundation to this wonderful HDL language, this is it!

I looked at this book to learn Verilog 2001. This book is not it. The book doesn't cover the most basic constructs of Verilog 2001 such as always @(*) and the reduced verbosity of entity declarations. Also, the author does not cross-reference a feature with what standard supports it. This makes it worthless as a reference for both the new and old standard. If you want to learn Verilog 2001, wait for a better book. If you want to learn the old standard, buy his 1st edition.

The 2nd Edition of this book should be renamed, "Verilog 2001 HDL". Palnitkar added Verilog 2001 to this edition but neglected to mention the difference between Verilog and Verilog 2001 in his text. For example in his 2nd edition he says that arrays can be declared with any number of dimensions. But he fails to add that is only true for Verilog 2001. Many simulators and synthesis tools don't support all of verilog 2001 yet so you may have trouble getting the example code working in a real design.

I read the book; it is a good one for reader to catch the idea quickly. But to use it as a reference book might not be a good idea. The topic organization is divided into basic usage section and advanced technique section, and kind of hard to locate for a certain issue. However, it is still worthy of reading as a beginner. The most things I like this book is it use example(s) to explain the concept.

Gives a very good introduction to Verilog HDL. Title is misleading because there isn't much synthesis covered. You won't get a whole lot of insight to the PLI either. If you don't know any Verilog, this book is a good place to start.

As a first book on Verilog this is not a good book. I could not find any thing I was looking for in the index. There is only about a quarter of a page on memories and only a four line example. Most of the examples were poor and incomplete. This book is not for beginners. I found about four other books that were good references, such as A Verilog HDL Primer, Third Edition by J. Bhasker and Verilog HDL: Digital Design and Modeling by Joseph Cavanagh. Both books have good examples and explanations. If your just starting out buy these two books and not Verilog HDL by Samir Palnitkar.

Like the other Verilog books I've read, this one seems to be a manual for those who wish to model rather than those who wish to synthesize actual circuits. The book concentrates too much on behavioral code and gate level design, neither of which are as important or as difficult as synthesizable code.