Verilog HDL Synthesis, A Practical Primer [Paperback]

J. Bhasker (Author)

Book Description

Publication Date: October 1998

With this book, you can:

- Start writing synthesizable Verilog models quickly.

- See what constructs are supported for synthesis and how these map to hardware so that you can get the desired logic.

- Learn techniques to help avoid having functional mismatches.

- Immediately start using many of the models for commonly used hardware elements described for your own use or modify these for your own application.

Editorial Reviews

Review

"Bhasker's book reveals a variety of situations where differences between simulation and synthesis semantics are bound to occur. These are carefully covered so that novice and experienced designers become aware of these hard to debug but, very common pitfalls" -- Carlos M. Roman, Bell Labs

"I find the book useful in illustrating examples of how the Verilog language may be used to design real and practical synthesizable models. It's also helpful that it warns the user of possible simulation/ synthesis mismatches. This clarifies the sim/syn issues for beginners." -- Jenjen Tiao, Lucent Technologies

"I've finished reading your book, I have to say I think you did an outstanding job ... I will be very comfortable recommending your book instead ... I really think this is your best book yet, good job!" -- Ken Coffman, VLSI designer

"Provides students and practicing logic designers with immediate access to well organized information about Verilog HDL synthesis. Easy to read and provides a large number of examples of synthesizable Verilog models" -- Vassilios Gerousis, Senior Staff Technologist, Motorola

"The book "A Verilog Synthesis Primer" is an excellent clear and concise guide for designing RTL synthesizable models in Verilog. It is an essential addition to design engineers' technical resourses." -- Douglas J. Smith, author of "HDL Chip Design."

"The example-driven driven approach used in the Verilog HDL Synthesis Primer makes it a valuable book for novice Verilog users." -- Egbert Molenkamp, University of Twente

"This book is ideally organized for teaching Verilog-based synthesis techniques, as it shows the reader not only what hardware results from various Verilog constructs, but how to tailor the Verilog to get the desired hardware. Copious pairings of examples with diagrams make clear the relationships between code and generated gates" -- Jim Vellenga, ViewLogic Systems

About the Author

J. Bhasker is the chair of the IEEE PAR 1364.1 Verilog Synthesis Interoperability Working Group that is working towards standardizing a Verilog subset for RTL synthesis. He is one of the main architects of the Archsyn synthesis system developed at Bell Labs. He has taught Verilog HDL and Verilog HDL synthesis to many AT&T / Lucent designers. He is also the author of the bestselling book "A Verilog HDL Primer"'.

Product Details

• Paperback: 215 pages
• Publisher: Star Galaxy Pub; 1 edition (October 1998)
• Language: English
• ISBN-10: 0965039153
• ISBN-13: 978-0965039154
• Product Dimensions: 8.8 x 6.9 x 0.7 inches
• Shipping Weight: 6.4 ounces (View shipping rates and policies)
• Average Customer Review: 4.3 out of 5 stars  See all reviews (7 customer reviews)
• Amazon Best Sellers Rank: #545,835 in Books (See Top 100 in Books)

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Customer Reviews

Most Helpful Customer Reviews

24 of 25 people found the following review helpful:

5.0 out of 5 stars Excellent and Practical guide for today's RTL design, February 4, 1999

By 

[e-mail] (Yokohama, Japan) - See all my reviews

This review is from: Verilog HDL Synthesis, A Practical Primer (Paperback)

This book gives many examples to help immediate application for practical design. Synthesis is much more important than simulation, because that the major reason of rapid increase of HDL designers is the recent availability of synthesis tool. However, many published books spend little effort for synthesis. This book is the first book that intensively focuses the synthesis in the user's view; how to desribe design to generate intended circuit. No complicated talk on CAD technology. The discussion on blocking vs non-blocking assignments is also valuable for an advancved understanding on the semantic consistency between synthesis and simulation.This book is a really excellent and practical guide for today's RTL design.

13 of 13 people found the following review helpful:

5.0 out of 5 stars A Synthesis Book...At Last, August 1, 2001

By 

ebonizer ramirez (Silicon Valley, USA) - See all my reviews

This review is from: Verilog HDL Synthesis, A Practical Primer (Paperback)

I write this review for two books: Verilog HDL Primer and Verilog HDL "SYNTEHSIS" Primer. Both books are primers, but serve the title very well. The books are straight to the point and do not "ramble" with grammar (ie. he tells you what it is you need to know and does not attempt to distract you). This is the book I use when I look for Verilog contructs for synthesis. The examples resemble closer to real world application including techniques in modeling digital systems. No comparison to the "other" Verilog text (Palnitkar). These two books complement one another. Another good verilog book is by Sternheim, but it is relatively expensive and hard to get.

10 of 10 people found the following review helpful:

4.0 out of 5 stars This is a very good (and short) book on Verilog synthesis, November 16, 2001

By A Customer

This review is from: Verilog HDL Synthesis, A Practical Primer (Paperback)

The author does a very good job of covering synthesizable Verilog. The numerous examples provide the reader with solid Verilog coding style guidelines. In addition, the author's discussion of blocking and non-blocking assignment statements for synthesizing combinational and sequential logic is very clear and concise. The only complaint I have about the book is its weak treatment of parameterizable design for synthesis. Despite the drawback, this is a very good reference and coding style guide for writing synthesizable Verilog.