Customer Reviews

Verilog HDL Synthesis, A Practical Primer

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This book gives many examples to help immediate application for practical design. Synthesis is much more important than simulation, because that the major reason of rapid increase of HDL designers is the recent availability of synthesis tool. However, many published books spend little effort for synthesis. This book is the first book that intensively focuses the synthesis in the user's view; how to desribe design to generate intended circuit. No complicated talk on CAD technology. The discussion on blocking vs non-blocking assignments is also valuable for an advancved understanding on the semantic consistency between synthesis and simulation.This book is a really excellent and practical guide for today's RTL design.

I write this review for two books: Verilog HDL Primer and Verilog HDL "SYNTEHSIS" Primer. Both books are primers, but serve the title very well. The books are straight to the point and do not "ramble" with grammar (ie. he tells you what it is you need to know and does not attempt to distract you). This is the book I use when I look for Verilog contructs for synthesis. The examples resemble closer to real world application including techniques in modeling digital systems. No comparison to the "other" Verilog text (Palnitkar). These two books complement one another. Another good verilog book is by Sternheim, but it is relatively expensive and hard to get.

The author does a very good job of covering synthesizable Verilog. The numerous examples provide the reader with solid Verilog coding style guidelines. In addition, the author's discussion of blocking and non-blocking assignment statements for synthesizing combinational and sequential logic is very clear and concise. The only complaint I have about the book is its weak treatment of parameterizable design for synthesis. Despite the drawback, this is a very good reference and coding style guide for writing synthesizable Verilog.

I used the book with the XILINX version of ModelSim, a Verilog Simulator.
My goal was to be able to generate synthsizable Verilog without a lot of experimentation.
The style is by example. It is a good source of useful Verilog coding.
It is assumed you have some background in Verilog.
The book could use some tables on logic operators.
I think people who want to learn and use Verilog for synthesizable designs would benifit from having this book close at hand. It could be a really useful text for college students.

The 1998 copyright date is at least six Moore generations ago, as of this writing. CAD tools, and synthesis in particualar, have advanced hugely since then, so much of Bhasker's advice simply isn't needed any more - compilers have gotten lots smarter about common subexpressions, for example, so things like manually factoring them out won't have nearly the impact today that they did then.

Also, for some reason, Bhasker seemed to assume only synthesis straight to silicon when, even then, FPGAs were a significant part of the logic market. In the decade since, synthesis for FPGAs has become the dominant model. That means that synthesis tools need to infer uses of block RAMs, hard multipliers, and other special functions from the HDL code, things outside of Bhasker's discussion. The biggest problem might be timing - it just never gets mentioned, even though it's a major headache in most non-trivial designs.

Perhaps, in its day, thie offered a reasonable introduction for the digital ASIC designer. That day passed, and this just doesn't meet the needs of most current logic implementors.

-- wiredweird

This book is an excellant reference for anyone writing Verilog for synthesis. I found the examples useful and complete.

This is the best book about the Verilog Synthesis. The book is very practical, and I immediately applied many examples into my work....