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Verilog HDL (paperback) (2nd Edition) 2nd Edition

3.7 out of 5 stars 37 customer reviews
ISBN-13: 978-0132599702
ISBN-10: 0132599708
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Editorial Reviews

From the Inside Flap

During my earliest experience with Verilog HDL, I was looking for a book that could give me a "jump start" on using Verilog HDL. I wanted to learn basic digital design paradigms and the necessary Verilog HDL constructs that would help me build small digital circuits, using Verilog and run simulations. After I had gained some experience with building basic Verilog models, I wanted to learn to use Verilog HDL to build larger designs. At that time I was searching for a book that broadly discussed advanced Verilog-based digital design concepts and real digital design methodologies. Finally, when I had gained enough experience with digital design and verification of real IC chips, though manuals of Verilog-based products were available, from time to time, I felt the need for a Verilog HDL book that would act as a handy reference. This book emphasizes breadth rather than depth. The book imparts to the reader a working knowledge of a broad variety of Verilog-based topics, thus giving the reader a global understanding of Verilog HDL-based design. The book leaves the in-depth coverage of each topic to the Verilog HDL language reference manual and the reference manuals of the individual Verilog-based products. This book should be classified not only as a Verilog HDL book but, more generally, as a digital design book. It important to realize that Verilog HDL is only a tool used in digital design. It is the means to an end- the digital IC chip. Therefore, this book stresses the practical design perspective more than the mere language aspects of Verilog HDL. With HDL-based digital design becoming popular, no digital designer can afford to ignore HDLs.

Who Should Use This Book...
The book is intended primarily for beginners and intermediate-level Verilog users. However, for advanced Verilog users, the broad coverage of topics makes it an excellent reference book to be used in conjunction with the manuals and training materials of Verilog-based products. The book presents a logical progression of Verilog HDL-based topics. It starts with the basics, such as HDL-based design methodologies, and then gradually builds on the basics to eventually reach advanced topics, such as PLI or logic synthesis. Thus, the book is useful to Verilog users with varying levels of expertise as explained below.

Students in logic design courses at universities Part 1 of this book is ideal for a foundation semester course in Verilog HDL-based logic design. Students are exposed to hierarchical modeling concepts, basic Verilog constructs and modeling techniques, and the necessary knowledge to write small models and run simulations.

New Verilog users in the industry Companies are moving to Verilog HDL- based design. Part 1 of this book is a perfect jump start for designers who want to orient their skills toward HDL-based design.

Users with basic Verilog knowledge who need to understand advanced concepts Part 2 of this book discusses advanced concepts, such as UDPs, timing simulation, PLI, and logic synthesis, which are necessary for graduation from small Verilog models to larger designs.

Verilog experts

All Verilog topics are covered, from the basics modeling constructs to advanced topics like PLIs and logic synthesis. For Verilog experts, this book is a handy reference to be used along with the reference manuals. The material in the book sometimes leans toward an Application Specific Integrated Circuit (ASIC) design methodology. However, the concepts explained in the book are general enough to be applicable to the design of FPGAs, PALs, buses, boards, and systems. The book uses Medium Scale Integration (MSI) logic examples to simplify discussion. The same concepts apply to VLSI designs.

How This Book Is Organized:
This book is organized into three parts. Part 1, Basic Verilog Topics, covers all information that a new user needs to build small Verilog models and run simulations. Note that in Part 1, gate-level modeling is addressed before behavioral modeling. I have chosen to do so because I think that it is easier for a new user to see a 1-1 correspondence between gate- level circuits and equivalent Verilog descriptions. Once gate-level modeling is understood, a new user can move to higher levels of abstraction, like data flow modeling and behavioral modeling, without losing sight of the fact that Verilog HDL is a language for digital design and is not a programming language. Thus, a new user starts off with the idea that Verilog is a language for digital design. New users who start with behavioral modeling often tend to write Verilog the way they write their C programs. They sometimes lose sight of the fact that they are trying to represent hardware circuits by using Verilog. Part 1 contains nine chapters.

Part 2, Advanced Verilog Topics, contains the advanced concepts a Verilog user needs to know to graduate from small Verilog models to larger designs. Advanced topics such as timing simulation, switch-level modeling, UDPs, PLI, and logic synthesis are covered. Part 2 contains five chapters. Part 3, Appendices, contains information useful as a reference. Useful information, such as strength-level modeling, list of PLI routines, formal syntax definition, Verilog tidbits, and large Verilog examples is included. Part 3 contains six appendices.

Conventions Used in This Book. Table\x11PR-1 describes the type changes and symbols used in this book. Table\x11PR-1 Typographic Conventions Typeface or Symbol
Examples: AaBbCc123 Keywords, system tasks and compiler directives that are a part of Verilog HDL and, nand, $display, `define AaBbCc123 Emphasis. cell characterization, instantiation AaBbCc123 Names of signals, modules, ports, etc. fulladd4, D_FF, out A few other conventions need to be clarified.

In the book, use of Verilog and Verilog HDL refers to the "Verilog Hardware Description Language." Any reference to a Verilog-based simulator is specifically mentioned, using words such as Verilog simulator or trademarks such as Verilog-XL or VCS.

The word designer is used frequently in the book to emphasize the digital design perspective. However, it is a general term used to refer to a Verilog HDL user. --This text refers to an out of print or unavailable edition of this title.

From the Back Cover

VERILOG HDL, Second Edition by Samir Palnitkar With a Foreword by Prabhu Goel

Written forboth experienced and new users, this book gives you broad coverage of VerilogHDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspects. The informationpresented is fully compliant with the IEEE 1364-2001 Verilog HDL standard.

Among its many features, this edition–

  • Describes state-of-the-art verification methodologies

  • Provides full coverage of gate, dataflow (RTL), behavioral and switch modeling

  • Introduces you to the Programming Language Interface (PLI)

  • Describes logic synthesis methodologies

  • Explains timing and delay simulation

  • Discusses user-defined primitives

  • Offers many practical modeling tips

Includes over 300 illustrations, examples, and exercises, and a Verilog resource list.Learning objectives and summaries are provided for each chapter.

About the CD-ROM

The CD-ROM contains a Verilog simulator with agraphical user interface and the source code for the examples in the book.

Whatpeople are saying about Verilog HDL

“Mr.Palnitkar illustrates how and why Verilog HDL is used to develop today’smost complex digital designs. This book is valuable to both the novice and theexperienced Verilog user. I highly recommend it to anyone exploring Verilogbased design."

–RajeevMadhavan, Chairman and CEO, Magma Design Automation

“Thisbook is unique in its breadth of information on Verilog and Verilog-relatedtopics. It is fully compliant with the IEEE 1364-2001 standard, contains allthe information that you need on the basics, and devotes several chapters toadvanced topics such as verification, PLI, synthesis and modelingtechniques.”

–MichaelMcNamara, Chair, IEEE 1364-2001 Verilog Standards Organization

Thishas been my favorite Verilog book since I picked it up in college. It is theonly book that covers practical Verilog. A must have for beginners andexperts.”

–BerendOzceri, Design Engineer, Cisco Systems, Inc.

“Simple,logical and well-organized material with plenty of illustrations, makes this anideal textbook.”

–Arun K. Somani, Jerry R. Junkins Chair Professor,Department of Electrical and Computer Engineering, Iowa State University, Ames


Professional Technical Reference

Upper Saddle River, NJ 07458


ISBN: 0-13-044911-3


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Product Details

  • Paperback: 496 pages
  • Publisher: Prentice Hall; 2 edition (March 3, 2003)
  • Language: English
  • ISBN-10: 0132599708
  • ISBN-13: 978-0132599702
  • Product Dimensions: 6.9 x 1.2 x 9.4 inches
  • Shipping Weight: 1.8 pounds (View shipping rates and policies)
  • Average Customer Review: 3.7 out of 5 stars  See all reviews (37 customer reviews)
  • Amazon Best Sellers Rank: #674,070 in Books (See Top 100 in Books)

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Customer Reviews

Top Customer Reviews

Format: Hardcover
This book is suitable for its time, but the contents are more intended for Verilog models. It talks a lot about the Verilog syntax; however, the title mislead me - VERY LITTLE discussion about Verilog for Synthesis. There is only one chapter devoted to systhesis, and this chapter happens to be the LAST chapter of the book.
Don't get me wrong. This is a good book for beginners in Verilog HDL. It is a "MIX-BAG" of syntax only for understanding (NOT synthesis). After reading this book, one should be familiar with the application of Verilog for Simulation and Modeling, but one may still have to get a synthesis book or training to further utilize the power of Verilog for FPGA or ASIC design (I am an FPGA designer). I gave it 3 stars due a misleading title and the fact that only a single chapter was devoted to synthesis topic.
One topic bothers me. Why would someone use Verilog HDL to model the Transisor Level (he calls it the switch level)? Isn't this the reason SPICE programs were designed to do? Besides that, Verilog HDL is still YET to add ANALOG capabilities.
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Format: Hardcover
As a first book on Verilog this is not a good book. I could not find any thing I was looking for in the index. There is only about a quarter of a page on memories and only a four line example. Most of the examples were poor and incomplete. This book is not for beginners. I found about four other books that were good references, such as A Verilog HDL Primer, Third Edition by J. Bhasker and Verilog HDL: Digital Design and Modeling by Joseph Cavanagh. Both books have good examples and explanations. If your just starting out buy these two books and not Verilog HDL by Samir Palnitkar.
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Format: Hardcover
This book starts from very basic knowledge of Verilog. It assumes no prior knowledge of the language. It starts from explaining the different data types of Verilog with very clear examples. Then it shows you how to create a module and why is it important to divide your design into several modules. Then it teaches you how to create a circuit at gate level modeling. The schematics of the the code is given in the book, so you can clearly see the relationship between the schematics and its corresponding Verilog code. Then it moves to data flow modeling, again with very clear examples. After that, it moves to Behavioral Modeling. This the only book that gives me a very good understanding of always block, initial block, reg data type, and most importantly blocking and non blocking assignment. It has excellent example of how to create a state machine. The rest of the book teach you some tips that will make it easier for you to write your code. It also has some very good examples of how to create a testbench. Almost every example has its own testbench. So, you will learn how to create a testbench as you read the book from the very beginning. I only have 2 complains of the book. One is it doesn't tell you which part of the language is synthesizable until near the end of the book. Second is it doesn't tell you which part of the examples is the new features in Verilog 2001. This could be problematic if your simulator and synthesis tool does not fully support Verilog 2001. But other than that, I am fully satisfied. When I first learned Verilog, I browsed many other books. And this one is absolutely the best one. Without this book, I won't be able to finish my projects ahead of time with an A+. Good job Mr. Palnitkar!
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Format: Hardcover
The early chapters are an excellent guide to the syntax and wiring connections, they clearly outline potential pitfalls. Chapters 5 & 6 cover designs from too low a level. I'm sure other real-world designers will agree that modeling a flip-flop with gates just flops. I'm on Ch. 7 now and except for a reference on (min:typ:max) back to (yech!) chapter 5 the author finally gets back to real world design and synthesis (though he doesn't differentiate). Design for synthesis is a different animal than test design and where they diverge should be hi-lighted. But the explanations are clear and eventually the important levels of verilog design are covered. So if read thoughtfully it is a very good intro to verilog, but beware the useless filler.
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Format: Hardcover
I used this book to learn Verilog and if you read it from beginning to end, you might learn the gist of the language...but that's it. The book is virtually useless as any kind of reference source. The index is almost unusable (if you want to learn about the keywords "fork" or "join", for example, good luck. They aren't even listed in the index, along with just about everything else). Descriptions of how the language works are cryptic and overly brief, though the examples are sometimes helpful.

I seldom write reviews of books, but this one has annoyed me so much that I felt compelled to do so.

All in all, it's better than no book at all, but not much better.
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Format: Hardcover
Like the other Verilog books I've read, this one seems to be a manual for those who wish to model rather than those who wish to synthesize actual circuits. The book concentrates too much on behavioral code and gate level design, neither of which are as important or as difficult as synthesizable code.
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By A Customer on April 24, 2003
Format: Hardcover
The 2nd Edition of this book should be renamed, "Verilog 2001 HDL". Palnitkar added Verilog 2001 to this edition but neglected to mention the difference between Verilog and Verilog 2001 in his text. For example in his 2nd edition he says that arrays can be declared with any number of dimensions. But he fails to add that is only true for Verilog 2001. Many simulators and synthesis tools don't support all of verilog 2001 yet so you may have trouble getting the example code working in a real design.
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Verilog HDL (paperback) (2nd Edition)
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