From the Inside Flap
Who Should Use This Book...
The book is intended primarily for beginners and intermediate-level Verilog users. However, for advanced Verilog users, the broad coverage of topics makes it an excellent reference book to be used in conjunction with the manuals and training materials of Verilog-based products. The book presents a logical progression of Verilog HDL-based topics. It starts with the basics, such as HDL-based design methodologies, and then gradually builds on the basics to eventually reach advanced topics, such as PLI or logic synthesis. Thus, the book is useful to Verilog users with varying levels of expertise as explained below.
Students in logic design courses at universities Part 1 of this book is ideal for a foundation semester course in Verilog HDL-based logic design. Students are exposed to hierarchical modeling concepts, basic Verilog constructs and modeling techniques, and the necessary knowledge to write small models and run simulations.
New Verilog users in the industry Companies are moving to Verilog HDL- based design. Part 1 of this book is a perfect jump start for designers who want to orient their skills toward HDL-based design.
Users with basic Verilog knowledge who need to understand advanced concepts Part 2 of this book discusses advanced concepts, such as UDPs, timing simulation, PLI, and logic synthesis, which are necessary for graduation from small Verilog models to larger designs.
All Verilog topics are covered, from the basics modeling constructs to advanced topics like PLIs and logic synthesis. For Verilog experts, this book is a handy reference to be used along with the reference manuals. The material in the book sometimes leans toward an Application Specific Integrated Circuit (ASIC) design methodology. However, the concepts explained in the book are general enough to be applicable to the design of FPGAs, PALs, buses, boards, and systems. The book uses Medium Scale Integration (MSI) logic examples to simplify discussion. The same concepts apply to VLSI designs.
How This Book Is Organized:
This book is organized into three parts. Part 1, Basic Verilog Topics, covers all information that a new user needs to build small Verilog models and run simulations. Note that in Part 1, gate-level modeling is addressed before behavioral modeling. I have chosen to do so because I think that it is easier for a new user to see a 1-1 correspondence between gate- level circuits and equivalent Verilog descriptions. Once gate-level modeling is understood, a new user can move to higher levels of abstraction, like data flow modeling and behavioral modeling, without losing sight of the fact that Verilog HDL is a language for digital design and is not a programming language. Thus, a new user starts off with the idea that Verilog is a language for digital design. New users who start with behavioral modeling often tend to write Verilog the way they write their C programs. They sometimes lose sight of the fact that they are trying to represent hardware circuits by using Verilog. Part 1 contains nine chapters.
Part 2, Advanced Verilog Topics, contains the advanced concepts a Verilog user needs to know to graduate from small Verilog models to larger designs. Advanced topics such as timing simulation, switch-level modeling, UDPs, PLI, and logic synthesis are covered. Part 2 contains five chapters. Part 3, Appendices, contains information useful as a reference. Useful information, such as strength-level modeling, list of PLI routines, formal syntax definition, Verilog tidbits, and large Verilog examples is included. Part 3 contains six appendices.
Conventions Used in This Book. Table\x11PR-1 describes the type changes and symbols used in this book. Table\x11PR-1 Typographic Conventions Typeface or Symbol
Examples: AaBbCc123 Keywords, system tasks and compiler directives that are a part of Verilog HDL and, nand, $display, `define AaBbCc123 Emphasis. cell characterization, instantiation AaBbCc123 Names of signals, modules, ports, etc. fulladd4, D_FF, out A few other conventions need to be clarified.
In the book, use of Verilog and Verilog HDL refers to the "Verilog Hardware Description Language." Any reference to a Verilog-based simulator is specifically mentioned, using words such as Verilog simulator or trademarks such as Verilog-XL or VCS.
The word designer is used frequently in the book to emphasize the digital design perspective. However, it is a general term used to refer to a Verilog HDL user. --This text refers to an out of print or unavailable edition of this title.
From the Back Cover
VERILOG HDL, Second Edition by Samir Palnitkar With a Foreword by Prabhu Goel
Written forboth experienced and new users, this book gives you broad coverage of VerilogHDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspects. The informationpresented is fully compliant with the IEEE 1364-2001 Verilog HDL standard.
Among its many features, this edition–
Describes state-of-the-art verification methodologies
Provides full coverage of gate, dataflow (RTL), behavioral and switch modeling
Introduces you to the Programming Language Interface (PLI)
Describes logic synthesis methodologies
Explains timing and delay simulation
Discusses user-defined primitives
Offers many practical modeling tips
Includes over 300 illustrations, examples, and exercises, and a Verilog resource list.Learning objectives and summaries are provided for each chapter.About the CD-ROM
The CD-ROM contains a Verilog simulator with agraphical user interface and the source code for the examples in the book.
Whatpeople are saying about Verilog HDL–
“Mr.Palnitkar illustrates how and why Verilog HDL is used to develop today’smost complex digital designs. This book is valuable to both the novice and theexperienced Verilog user. I highly recommend it to anyone exploring Verilogbased design."
–RajeevMadhavan, Chairman and CEO, Magma Design Automation
“Thisbook is unique in its breadth of information on Verilog and Verilog-relatedtopics. It is fully compliant with the IEEE 1364-2001 standard, contains allthe information that you need on the basics, and devotes several chapters toadvanced topics such as verification, PLI, synthesis and modelingtechniques.”
–MichaelMcNamara, Chair, IEEE 1364-2001 Verilog Standards Organization
Thishas been my favorite Verilog book since I picked it up in college. It is theonly book that covers practical Verilog. A must have for beginners andexperts.”
–BerendOzceri, Design Engineer, Cisco Systems, Inc.
“Simple,logical and well-organized material with plenty of illustrations, makes this anideal textbook.”
–Arun K. Somani, Jerry R. Junkins Chair Professor,Department of Electrical and Computer Engineering, Iowa State University, Ames
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