Customer Reviews

Verilog Styles for Synthesis of Digital Systems

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4 star:		(0)
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1 star:		(2)

 

 

I was very excited when I saw this book hoping it'd open me all of the secrets of not-known-until-now world of HDL Synthesis. How wrong I was. The title is very misleading, the book spends just a few pages on synthesis. Overall, this book might be useful for a novice, but even for me, an undergrad ECE major, it turned out to be almost useless. It contains minimum of factual information, often outdated(and this is critical in the ECE world), and only slightly touches the surface on a number of topics it tries to cover. I think the authors whould have concentrated on something specific, instead of giving "what happened in Computer Engineering in last 15 years" review.

I have been searching for an Verilog book that will allow me to get up to speed quickly for an particular project. I wanted something that presented the syntax of the language in an clear manner but more importantly would give me an methodology to allow me to use Verilog in the design of an FPGA. This book seems to have "the right stuff". This book along with "Verilog HDL" by Samir Palnitkar seem to be the best that I have seen for learning Verilog

This book very concisely explains how to synthesizable verilog code. A beginner with no idea of HDL concepts might get overwhelmed. I would recommend beginners to start with Verilog HDL by Samir Palnitkar and then move on to this book.

Definitely a must have.

I have been a user of VHDL for the last three years and am now beginning to use Verilog, mostly because I am now doing ASIC development. For the new Verilog user, this book is excellent because it covers the gamut for an HDL and FPGA designer -- the syntax of the language,the difference between structural and behavioral constructs, simulation, hierarchical design, and of course the ubiqituous State Machine. Also included are some sections on targeting different types of technology, including standard cell. I found this book quite useful compared to other Verilog books I have purchased.

This is the worst book ever to use as a textbook for teaching Verilog. I was very happy learning the book because it's thin and used the knowledge to design digital systems. But as I spend more time doing design, I find MORE bugs and glitches based on the knowledge I learn from this book. It's a book that you MUST AVOID using because I believe the authors themselves probably didn't even design a single working ASIC chip. Few proofs of my complains include: 1) The authors are confused between using blocking and nonblocking assign (=, <=). As an expert in program and a hardcore CS student, I thought these would be the same until much later I do more digital design and DEBUGGING tons of problems. The authors actually used <= or nonblocking assignment in combinational blocks. 2) Finite state machines are horrible. They'll teach you the WRONG thing. For example, one-hot encoding makes absolute no sense when you use the whole N-bits for comparison in the case statement instead of just ONE-bit (on page 114). The authors said classical two always blocks in FSM are not good and encouraged one always block using implicit state machines. Believe you'll run into nightmare of debugging those waveforms in your digital design if you follow their philosophy. Not only this book is bad but it teaches the wrong thing, the wrong way of design digital system. If you want destroy a project, then you must buy this book to design a broken digital system. I recommend reading free stuff from sunburst design Cliff Cummings to unlearn these wrongful things. A horrible horrible book that wasted so much of my time in designing and debugging. It wasted much more $$ (thousands of dollars for bad design chip) than the $65 I paid for the book.