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Verilog and SystemVerilog Gotchas: 101 Common Coding Errors and How to Avoid Them Paperback – November 5, 2010

ISBN-13: 978-1441944023 ISBN-10: 1441944028 Edition: Softcover reprint of hardcover 1st ed. 2007

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Verilog and SystemVerilog Gotchas: 101 Common Coding Errors and How to Avoid Them + SystemVerilog for Verification: A Guide to Learning the Testbench Language Features + SystemVerilog for Design Second Edition: A Guide to Using SystemVerilog for Hardware Design and Modeling
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Product Details

  • Paperback: 218 pages
  • Publisher: Springer; Softcover reprint of hardcover 1st ed. 2007 edition (November 5, 2010)
  • Language: English
  • ISBN-10: 1441944028
  • ISBN-13: 978-1441944023
  • Product Dimensions: 6.1 x 0.5 x 9.2 inches
  • Shipping Weight: 10.4 ounces (View shipping rates and policies)
  • Average Customer Review: 4.5 out of 5 stars  See all reviews (2 customer reviews)
  • Amazon Best Sellers Rank: #2,603,151 in Books (See Top 100 in Books)

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4 of 4 people found the following review helpful By Mike K. on November 7, 2008
Format: Hardcover
Verilog may appear to be "simple" for beginner because it is a loosely-typed language and its syntax is somewhat to that of C. In reality, Verilog is really a complex language and many intricate details and features are buried in the language standard (i.e., LRM, Language Reference Manual). Sometimes these details are counter-intuitive and cause unexpected behaviors (for example, the expressions "(a+b)>>1" and "(0+a+b)>>1" are likely to return different results). This book systematically lists and discusses these gotchas, provides guidelines to avoid these traps, and helps you to develop reliable and robust Verilog codes. It can save you many, many debugging hours down the road. Though somewhat expensive, this book is a valuable reference for serious Verilog developers. A simplified version of this book appears as a conference paper. You can search the web and take a look and decide whether it fits you need.
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2 of 2 people found the following review helpful By Melanie D. Typaldos on December 25, 2010
Format: Paperback Verified Purchase
Just started writing SystemVerilog coming from a background of Verilog and C++ but the Verilog was a bit stale. There are a lot of things about SystemVerilog that seem counterintuitive from C++, such as automatic vs. static variables, that everything is essentially pointers, scoping rules, the way inheritance works. As I started reading the gotchas in this book, I realized I had already made several of them. I still make gotchas that I've read about but at least I recognize them.
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