Writing Testbenches: Functional Verification of HDL Models, Second Edition (Hardcover)

~ (Author) "Verification is not a testbench, nor is it a series of testbenches..." (more)
Key Phrases: synthesizeable subset, debug testcases, temporal sampling event, Open Vera, Specman Elite, Utopia Level (more...)

Editorial Reviews

Review

"Brilliant. Janick Bergeron has built on his ground-breaking first version of Writing Testbenches in this second edition..." (Grant Martin, Fellow, Cadence Berkeley Labs) "In the latest edition, Mr. Bergeron continues to keep pace with the industry while providing world-class solutions to the verification problem..."(Chris Macinonski, Senior Engineer, Qualis Design Corp.) "Many companies out there now owe their current verification methodologies to this book. From it they have learned the secrets of efficiency, effectiveness and re-use as they apply to verification..." (Brian Bailey, Chief Technologist, Mentor Graphics Corp.) "A must have bible for understanding verification issues and techniques with HDLs and HVLs, and for writing effective, readable and reusable testbenches within a best-in-class verification process." (Ben Cohen, VhdlCohen Training)

`Brilliant. Janick Bergeron has built on his ground-breaking first version of Writing Testbenches in this second edition...' -- Grant Martin, Fellow, Cadence Berkeley Labs

Product Description

The Second Edition of Writing Testbenches, Functional Verification of HDL Models presents the latest verification techniques to produce fully functional first silicon ASICs, systems-on-a-chip (SoC), boards and entire systems.

From the Foreword: Building on the first edition, " ...the most successful and popular contemporary verification textbook", the author raises the verification level of abstraction by introducing coverage-driven constrained random transaction-level self-checking testbenches - all made possible through the introduction of hardware verification languages (HVLs) such as e from Verisity and OpenVera from Synopsys...." Harry Foster, Chief Architect, Verplex Systems, Inc. Topics included in the new Second Edition: + Discussions on OpenVera and e; + approaches for writing constrainable random stimulus generators; + strategies for making testbenches self-checking; + a clear blueprint of a verification process that aims for first time success; + recent advances in functional verification such as coverage-driven verification process; + VHDL and Verilog language semantics; + the semantics are presented in new verification-oriented languages + techniques for applying stimulus and monitoring the response of a design; + behavioral modeling using non-synthesizeable constructs and coding style; + updated for Verilog 2001.

Product Details

• Hardcover: 512 pages
• Publisher: Springer; 2nd edition (February 1, 2003)
• Language: English
• ISBN-10: 1402074018
• ISBN-13: 978-1402074011
• Product Dimensions: 9.3 x 6.4 x 1.1 inches
• Shipping Weight: 1.8 pounds (View shipping rates and policies)
• Average Customer Review: 3.8 out of 5 stars  See all reviews (10 customer reviews)
• Amazon.com Sales Rank: #319,365 in Books (See Bestsellers in Books)

Customer Reviews

Most Helpful Customer Reviews

8 of 9 people found the following review helpful:

4.0 out of 5 stars Great content - can't wait for next edition, May 27, 2003

By	Frank Motta "fmotta" (Fremont, CA United States) - See all my reviews (REAL NAME)

This review is from: Writing Testbenches - Functional Verification of HDL Models (Hardcover)

I loved the book and it provided much information I needed - in a convoluted manner. I'm sure that Janick will improve upon this in the next edition and provide examples we all can use.

Thank you for the book and it's content - To my knowledge 15 people I know have purchased it upon my recommendation.

5 of 5 people found the following review helpful:

3.0 out of 5 stars Some interesting parts, but mostly a collection of 'tricks'., June 1, 2005

By	Mark Pontius "mpontius2" (Irvine, CA United States) - See all my reviews (REAL NAME)

This book covers many facets of the task of creating testbenches. However, it doesn't seem to follow a very well thought out plan, and there are holes in the coverage.

Most of the book is a 'tips and tricks' coverage of how to get each language to do what it wasn't designed to do. He walks through various situations and says that something is easy to do in Specman (shows a short code fragment), but then goes into long detail in how to get around VHDL's limitations and get the same result. I realize these are probably pretty cool tricks, but not at all the approach for me (a beginner to writing sizable testbenches). If he kept up the coverage of all 4 languages throughout, it might be useful, but the focus shifts from language to language at whim. You won't learn how to write a testbench as much as you will learn some pitfalls to avoid.

One more gripe before I get to the parts I liked. Each chapter ends with a summary. The summary lists the author's favorite tricks, not a summary of the whole chapter. I found these to be not at all helpful in either deciding whether to read the chapter, or as a review of what was covered.

I did like the explanations of:
-- The importance of verification (now I know why I was hired)
-- Overview of all the lingo (I can sound like I know what I'm talking about now, even if I don't)
-- Merits of the various types of coverage (code/functional/transition ...)
-- Aspect Oriented Programming (e) and why it is useful (cool stuff!)
-- Using coverage to drive a random bench

That is only about 10% of the book, however. That 10% was really pretty good.

I see one of the other reviewers complained about lack of downloadable sourcecode. It is available at www.janick.bergeron.com/wtb along with an extensive errata list (I'd recommend taking the hour or so and marking up your book before reading).

I still give the book 3 stars, since it is the only verification book I've found, and I did really like parts of it. I read the book front to back, and would not particularly recommend this to others. Pick the parts that interest you, and skip the rest.

7 of 8 people found the following review helpful:

3.0 out of 5 stars Great start but needs work, October 19, 2001

By	Niel Slaughter (Austin, TX United States) - See all my reviews

This review is from: Writing Testbenches - Functional Verification of HDL Models (Hardcover)

It is great that we, as verification engineers, finally have a book focusing on streamlining and improving the verification process. This book covers all the basics for building a verification plan, implementing it, and maintaining it. It also includes a very large compliment of examples right alongside the concepts to improve understanding. However, it is unfortunate that the author is caught not following his own principles in each example. I feel that I would learn his principles better through repetition, where each example builds on the concepts already presented. He presents bus functional models in one chapter, then starts again at the top in the next. This makes it hard for me to see the big picture. One large example at the end could make it easier for me to see all his principles together in one testbench. Otherwise I'm stuck taking notes...