Customer Reviews

Writing Testbenches: Functional Verification of HDL Models, Second Edition

5 star:		(4)
4 star:		(2)
3 star:		(3)
2 star:		(0)
1 star:		(1)

 

 

This book covers many facets of the task of creating testbenches. However, it doesn't seem to follow a very well thought out plan, and there are holes in the coverage.

Most of the book is a 'tips and tricks' coverage of how to get each language to do what it wasn't designed to do. He walks through various situations and says that something is easy to do in Specman (shows a short code fragment), but then goes into long detail in how to get around VHDL's limitations and get the same result. I realize these are probably pretty cool tricks, but not at all the approach for me (a beginner to writing sizable testbenches). If he kept up the coverage of all 4 languages throughout, it might be useful, but the focus shifts from language to language at whim. You won't learn how to write a testbench as much as you will learn some pitfalls to avoid.

One more gripe before I get to the parts I liked. Each chapter ends with a summary. The summary lists the author's favorite tricks, not a summary of the whole chapter. I found these to be not at all helpful in either deciding whether to read the chapter, or as a review of what was covered.

I did like the explanations of:
-- The importance of verification (now I know why I was hired)
-- Overview of all the lingo (I can sound like I know what I'm talking about now, even if I don't)
-- Merits of the various types of coverage (code/functional/transition ...)
-- Aspect Oriented Programming (e) and why it is useful (cool stuff!)
-- Using coverage to drive a random bench

That is only about 10% of the book, however. That 10% was really pretty good.

I see one of the other reviewers complained about lack of downloadable sourcecode. It is available at www.janick.bergeron.com/wtb along with an extensive errata list (I'd recommend taking the hour or so and marking up your book before reading).

I still give the book 3 stars, since it is the only verification book I've found, and I did really like parts of it. I read the book front to back, and would not particularly recommend this to others. Pick the parts that interest you, and skip the rest.

It is great that we, as verification engineers, finally have a book focusing on streamlining and improving the verification process. This book covers all the basics for building a verification plan, implementing it, and maintaining it. It also includes a very large compliment of examples right alongside the concepts to improve understanding. However, it is unfortunate that the author is caught not following his own principles in each example. I feel that I would learn his principles better through repetition, where each example builds on the concepts already presented. He presents bus functional models in one chapter, then starts again at the top in the next. This makes it hard for me to see the big picture. One large example at the end could make it easier for me to see all his principles together in one testbench. Otherwise I'm stuck taking notes...

I loved the book and it provided much information I needed - in a convoluted manner. I'm sure that Janick will improve upon this in the next edition and provide examples we all can use.

Thank you for the book and it's content - To my knowledge 15 people I know have purchased it upon my recommendation.

I have been working with VHDL and Verilog for years but this
is the first book that treats the subject of testbenches seriously and comprehensively in both language.
I collect books and this is one of the best written books in my shelf. Highly recommended

The book was great actually earning 3-1/2 out of 5 stars (the examples need to be debugged, tested and put online to merit 4 stars - I disagree with too many of the coding and methodology recommendations to award 5 stars). In my opinion, because the code examples are not full, because the code is not fully tested, and because not all examples are written in both Verilog and VHDL, the book is geared more to advanced users who can extrapolate the missing information and identify the mistakes in the code. The book will be best understood by experienced engineers who know both languages so that they can extract all of the relevant points. I disagree with a number of Janick's recommendations. A full review of this book is available on the sunburst-design web site.

This is the first technical book that I have read from cover-to-cover (minus a couple of the larger VHDL examples). I picked up a few techniques and tricks that I had not thought of before and that I intend to use. Although I may appear to be overly critical of Janick in my full review, I only do in-depth critiques of books that I deem worthy of recommending. Nice job, Janick!

In hardware development groups, the author points out that by 2000, from 60-80% of effort was in verification. But texts on VHDL rarely emphasise this. Instead, far more time is devoted to design. The creative focus is on the latter.

The author instead says that from project inception, one should strive to design for verification. All the way from netlists. He suggests how to construct self checking systems.

Surprisingly, initially, he nowhere discusses standard cells, and how you can use proven, tested standard cells in larger designs. But closer scrutiny of his arguments show that, implicitly, his techniques can be used to construct such cells, if they are not composed of smaller standard cells. It would have been nice if the index had an entry for standard cells, so that the reader could find this argument.

As a student in IC design, I am on the search for good books in the field and have made a considerable investment in a library. My budget is tight as a student and due to exchange rates, so good books are expensive for me.

Of the books purchased so far, this is book is genuinely unique and a worthwhile purchase. One of my mentor's advised that books on verification are rare, he thought there was one other, but I couldn't find it.

While I am still studying this book, I have found it to be the BEST I have purchased by far. It provides a unique insight into HDL design and verification. While it amazes many to read that so little work has been done in formalizing testing, a field consuming some 70 or more percent of design time, Janick provides an extremely valuable contribution.

The content covers both Verilog and VHDL coding so suits everyone and contains ample code in both languages to illustrate the points raised. It starts with a case study of a bridge that collapsed to demonstrate the need and continues in a logical and comprehensible manner.

The content builds in a way that a neophyte can easily understand, yet also would bore an experienced designer. Everyone in this field will learn useful skills

There are a lot of hackneyed superlatives one could use to describe this work. In restricting myself to one, I choose seminal.

The book has one minor drawback, my fourth print copy has a number of errors, in fact most of those from the second printing. Corrections are posted on the web site.

While I am reluctant to recommend books because it inflates expectations, I encourage every HDL designer and student to get this book and the corrections. It is a classic and will serve you very well for a long time!

I found this books extremely well written in terms of technical content and style. Yes, style. The words are efficient and almost leap off the page to convey the author's intent. I enjoyed the discussion of VHDL versus Verilog in the very beginning. The methods presented for testing and verification are very insightful. Probably one of the best HDL books out there, period.

This book has a great title and subject but that is all. The author is confused about languages and the subject matter. He shifts between many languages and for the most part of the book, he just complaining about each language. In terms of substance, there is none- really none. The book is very boring, a lot of jargon, definitions and worthless talk. You will not learn any language and you will not learn how to write test benches, heck, you will not want to write test benches - thank god I had already been doing test benches so I know it's not that boring and confusing as the book trying hard to make it. Save your self the money, time and furstration and just go online - there is a lot of info and tutorials about this subject which are more useful I found.

On the front lines of modern digital design, the challenges facing our industry are in implementing design reuse methods and the verification/validation of multi-million gate ASIC designs. Janick has been fighting these battles for many years and has written an excellent book, the first of its kind on the market. This is not a dry academic exercise; Janick reveals field-tested strategies, tips, and techniques. If you have any HDL books on your shelf, your collection is incomplete if you don't grab yourself a copy of this hot-selling book now.