Writing Testbenches using SystemVerilog [Hardcover]

Janick Bergeron (Author)

Book Description

ISBN-10: 0387292217 | ISBN-13: 978-0387292212 | Publication Date: February 10, 2006 | Edition: 1

Verification is too often approached in an ad hoc fashion. Visually inspecting simulation results is no longer feasible and the directed test-case methodology is reaching its limit. Moore's Law demands a productivity revolution in functional verification methodology. Writing Testbenches Using SystemVerilog offers a clear blueprint of a verification process that aims for first-time success using the SystemVerilog language. From simulators to source management tools, from specification to functional coverage, from I's and O's to high-level abstractions, from interfaces to bus-functional models, from transactions to self-checking testbenches, from directed testcases to constrained random generators, from behavioral models to regression suites, this book covers it all. Writing Testbenches Using SystemVerilog presents many of the functional verification features that were added to the Verilog language as part of SystemVerilog. Interfaces, virtual modports, classes, program blocks, clocking blocks and others SystemVerilog features are introduced within a coherent verification methodology and usage model. Writing Testbenches Using SystemVerilog introduces the reader to all elements of a modern, scalable verification methodology. It is an introduction and prelude to the verification methodology detailed in the Verification Methodology Manual for SystemVerilog.  It is a SystemVerilog version of the author's bestselling book Writing Testbenches: Functional Verification of HDL Models.

Editorial Reviews

Review

From the reviews: "The book provides verification engineers with an introduction to all elements of a modern, scalable verification environment and a foundation for adopting the advanced verification methodology detailed in the Verification Methodology Manual for SystemVerilog … . ‘Mr. Bergeon has once again written a book that is a standard-bearer for engineers tasked with verifying RTL and systems design’ … . the strategies and methodologies put forth by Mr. Bergeron has become more important to the success of every verification project." (EE Times, April, 2006)

From the Back Cover

Verification is too often approached in an ad hoc fashion. Visually inspecting simulation results is no longer feasible and the directed test-case methodology is reaching its limit. Moore's Law demands a productivity revolution in functional verification methodology. Writing Testbenches Using SystemVerilog offers a clear blueprint of a verification process that aims for first-time success using the SystemVerilog language. From simulators to source management tools, from specification to functional coverage, from I's and O's to high-level abstractions, from interfaces to bus-functional models, from transactions to self-checking testbenches, from directed testcases to constrained random generators, from behavioral models to regression suites, this book covers it all. Writing Testbenches Using SystemVerilog presents many of the functional verification features that were added to the Verilog language as part of SystemVerilog. Interfaces, virtual modports, classes, program blocks, clocking blocks and others SystemVerilog features are introduced within a coherent verification methodology and usage model. Writing Testbenches Using SystemVerilog introduces the reader to all elements of a modern, scalable verification methodology. It is an introduction and prelude to the verification methodology detailed in the Verification Methodology Manual for SystemVerilog.

Product Details

• Hardcover: 440 pages
• Publisher: Springer; 1 edition (February 10, 2006)
• Language: English
• ISBN-10: 0387292217
• ISBN-13: 978-0387292212
• Product Dimensions: 9.3 x 6.3 x 1.2 inches
• Shipping Weight: 1.9 pounds (View shipping rates and policies)
• Average Customer Review: 4.0 out of 5 stars  See all reviews (1 customer review)
• Amazon Best Sellers Rank: #1,362,133 in Books (See Top 100 in Books)

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Most Helpful Customer Reviews

23 of 23 people found the following review helpful:

4.0 out of 5 stars High-level, abstract approach and guidelines for the *experienced* Verification engineer, March 24, 2007

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hummingbird lover (California) - See all my reviews

This review is from: Writing Testbenches using SystemVerilog (Hardcover)

The book's title is a bit misleading. It does NOT teach you Systemverilog (for Verification) -- there is a separate book by Chris Spear ("Systemverilog for Verification") sold by the same publisher that focuses more on Systemverilog syntax and language features. This book is NOT a tutorial (i.e. beginner's guide) on how to write testbenches -- although it does go through the basic concepts, objectives, and challenges in writing maintainable/re-usable testbench environments, most of the textbook examples are too cryptic/advanced for an entry-level engineer.

So then, what does this book focus on? Well, the book focuses on general guidelines to writing re-usuable, high-level testbenches. The author uses Systemverilog as the language to communicate his concepts, but as I said before, the book does NOT teach you Systemverilog. (To the author's credit, he is very upfront about that in foreward/intro section.)

Who should read it:
Experienced verification engineers with a basic understanding of Systemverilog (and why it's superior to Verilog), who want some ideas/examples of how to deploy Systemverilog's advanced features (like classes, structs, random vars) in a verification environment.

What I liked:
The use of classes to encapsulate bus-functional-models (BFMs), how to create and manage variations of a basic BFM (using extended/derived classes), etc. He also shows how to combine randomization with classes, to create random stimulus-sequences.

What could have been improved:
I was hoping the book would cover SVA (systemverilog assertions) in greater depth, but I guess there are other books for that. He also superficially mentions "configurations" -- that is a feature in Verilog-2001 and VHDL-93. The book should have covered that in more depth (even though it's not a new Systemverilog feature), as it pertains to testcase management and organization.

What you should have:
You need a good background and experience in ASIC/RTL-verification -- this book is not an introduction to testbench concepts, or the Systemverilog language! You need to know some Systemverilog language, so either have a different book (like Chris Spear's "Systemverilog for Verification"), or the official IEEE Systemverilog 1800-2005 LRM next to your side. Though not necessary, it's helpful to have a basic understanding about object-oriented programming, because the examples in the book use Systemverilog's classes (and inheritance) to illustrate a lot of points. Object-oriented concepts would otherwise be foreign to most engineers working in the hardware field.

Ohter notes:
The book makes numerous references to the VMM (Verilog Methodology Manual), which is a separate book by the same author. VMM is probably as close to a 'canned' (i.e. pre-built) testbench environment as you can get. If you run Synopsys VCS in your company, then VMM is worth investigatation. Unfortunately, I've heard it doesn't run well on competing simulators (Cadence, Mentor), as Systemverilog support is still in its infancy.