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Editorial Reviews
Review
In the era of large systems embedded in a single system-on-chip (SOC) and fabricated continuously shrinking technologies, it is important to ensure correct behavior of the whole system. Electronic design and test engineers of today have to deal with these complex and heterogeneous systems (digital, mixed-signal, memory), but few have the possibility to study the whole field in a detailed and deep way. This book provides an extremely broad knowledge of the discipline, covering the fundamentals in detail, as well as the most recent and advanced concepts.
Michel Renovell, Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier (LIRMM), Montpellier, France
This book combines in a unique way insight into industry practices commonly found in commercial DFT tools but not discussed in textbooks, and a sound treatment of the future fundamentals. The comprehensive review of future test technology trends, including self-repair, soft error protection, MEMS testing, and RF testing, leads students and researchers to advanced DFT research.
Hans-Joachim Wunderlich, University of Stuttgart, Germany
Recent advances in semiconductor manufacturing have made design for testability (DFT) an essential part of nanometer designs. I am pleased to find a DFT textbook of this comprehensiveness that can serve both academic and professional needs.
Andre Ivanov, University of British Columbia, Canada
This is the most recent book covering all aspects of digital systems testing. It is a "must read" for anyone focused on learning modern test issues, test research, and test practices.
Kewal K. Saluja, University of Wisconsin-Madison
By covering the basic DFT theory and methodology on digital, memory, as well as analog and mixed-signal (AMS) testing, this book stands out as one best reference book that equips practitioners with testable SOC design skills.
Yihe Sun, Tsinghua University, Beijing, China
Michel Renovell, Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier (LIRMM), Montpellier, France
This book combines in a unique way insight into industry practices commonly found in commercial DFT tools but not discussed in textbooks, and a sound treatment of the future fundamentals. The comprehensive review of future test technology trends, including self-repair, soft error protection, MEMS testing, and RF testing, leads students and researchers to advanced DFT research.
Hans-Joachim Wunderlich, University of Stuttgart, Germany
Recent advances in semiconductor manufacturing have made design for testability (DFT) an essential part of nanometer designs. I am pleased to find a DFT textbook of this comprehensiveness that can serve both academic and professional needs.
Andre Ivanov, University of British Columbia, Canada
This is the most recent book covering all aspects of digital systems testing. It is a "must read" for anyone focused on learning modern test issues, test research, and test practices.
Kewal K. Saluja, University of Wisconsin-Madison
By covering the basic DFT theory and methodology on digital, memory, as well as analog and mixed-signal (AMS) testing, this book stands out as one best reference book that equips practitioners with testable SOC design skills.
Yihe Sun, Tsinghua University, Beijing, China
Book Description
The most up-to-date coverage available of VLSI Testing and Design-for-Testability!
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Inside This Book
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Key Phrases - Statistically Improbable Phrases (SIPs):
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linear decompressor, deductive fault simulation, scan design rules, fault coverage goal, available spare rows, failing syndrome, sequential fault simulation, untestable faults, bridging fault diagnosis, fault descriptors, nanometer age, transition count testing, memory access commands, scan extraction, adjacent scan cells, analog test buses, extended backward implications, redundancy analysis algorithms, scan input pin, test data volume, failing chip, space compactor, compressed stimulus, small delay defects, statistical fault analysis Key Phrases - Capitalized Phrases (CAPs): (learn more)
Test Conf, Test Symp, Test Comput, Design Automation Conf, New York, Europe Conf, Computer Design, Fault-Tolerant Computing, John Wiley, Kluwer Academic, Repeat Problem, Mentor Graphics, Prentice Hall, Shift Window Capture Window Shift Window, Agilent Technologies, Solid-State Circuits, Custom Integrated Circuits Conf, Intentionally Left Blank, Palo Alto, Semiconductor Industry Association, Texas Instruments, Cambridge University Press, Circuits Syst, Digest of Papers, San Jose New!
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Front Cover | Table of Contents | First Pages | Index | Surprise Me!
linear decompressor, deductive fault simulation, scan design rules, fault coverage goal, available spare rows, failing syndrome, sequential fault simulation, untestable faults, bridging fault diagnosis, fault descriptors, nanometer age, transition count testing, memory access commands, scan extraction, adjacent scan cells, analog test buses, extended backward implications, redundancy analysis algorithms, scan input pin, test data volume, failing chip, space compactor, compressed stimulus, small delay defects, statistical fault analysis Key Phrases - Capitalized Phrases (CAPs): (learn more)
Test Conf, Test Symp, Test Comput, Design Automation Conf, New York, Europe Conf, Computer Design, Fault-Tolerant Computing, John Wiley, Kluwer Academic, Repeat Problem, Mentor Graphics, Prentice Hall, Shift Window Capture Window Shift Window, Agilent Technologies, Solid-State Circuits, Custom Integrated Circuits Conf, Intentionally Left Blank, Palo Alto, Semiconductor Industry Association, Texas Instruments, Cambridge University Press, Circuits Syst, Digest of Papers, San Jose New!
Books on Related Topics | Concordance | Text Stats Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Index | Surprise Me!
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3% buy Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits (Frontiers in Electronic Testing Volume 17) $83.06 |
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