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System-on-Chip Test Architectures
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Editorial Reviews
Book Description
The comprehensive guide to modern system-on-chip testing and design for testability from bestselling author L.-T Wang!
Product Description
Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today?s overall product cost.
This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.
KEY FEATURES
* Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples.
* Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book.
* Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits.
* Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing.
* Practical problems at the end of each chapter for students.
The comprehensive guide to modern system-on-chip testing and design for testability from bestselling author L.-T Wang!
Product Description
Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today?s overall product cost.
This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.
KEY FEATURES
* Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples.
* Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book.
* Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits.
* Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing.
* Practical problems at the end of each chapter for students.
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Inside This Book
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Key Phrases - Statistically Improbable Phrases (SIPs):
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physical failures, probing technologies, probe hole, timing generator, power bus, small delay defects, fault coverage loss, test power dissipation, test data volume, sequential linear decompressor, transition fault tests, nonprogrammable cores, settable fields, comb accelerometer, memory readback, linear decompressors, analog wrapper, test bus architecture, wrapper scan chains, configuration memory bits, stability checker, value holding register, delay fault test generation, digital microfluidic biochips, shift clock frequency Key Phrases - Capitalized Phrases (CAPs): (learn more)
System-on-Chip Test Architectures, Test Conf, Test Symp, Computer-Aided Design, Design Automation Conf, Test of Computers, New York, Reliability Issues, Semiconductor Industry Association, Digital Test Architectures, San Jose, Network-on-Chip Test Architectures, Fault-Tolerant Design, Software-Based Self-Testing, Testing Aspects of Nanotechnology Trends, Low-Power Testing, Electronic Testing, Europe Conf, Morgan Kaufmann, Field Programmable Gate Array Testing, San Francisco, Solid-State Circuits, Computer Design, John Wiley, Design Practice Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Index | Surprise Me!
physical failures, probing technologies, probe hole, timing generator, power bus, small delay defects, fault coverage loss, test power dissipation, test data volume, sequential linear decompressor, transition fault tests, nonprogrammable cores, settable fields, comb accelerometer, memory readback, linear decompressors, analog wrapper, test bus architecture, wrapper scan chains, configuration memory bits, stability checker, value holding register, delay fault test generation, digital microfluidic biochips, shift clock frequency Key Phrases - Capitalized Phrases (CAPs): (learn more)
System-on-Chip Test Architectures, Test Conf, Test Symp, Computer-Aided Design, Design Automation Conf, Test of Computers, New York, Reliability Issues, Semiconductor Industry Association, Digital Test Architectures, San Jose, Network-on-Chip Test Architectures, Fault-Tolerant Design, Software-Based Self-Testing, Testing Aspects of Nanotechnology Trends, Low-Power Testing, Electronic Testing, Europe Conf, Morgan Kaufmann, Field Programmable Gate Array Testing, San Francisco, Solid-State Circuits, Computer Design, John Wiley, Design Practice Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Index | Surprise Me!
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