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Product Description
This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits. Anyone who needs to learn the concepts, principles, data structures, algorithms, and architectures of the EDA flow will benefit from this book.
- Covers complete spectrum of the EDA flow, from ESL design modeling to logic/test synthesis, verification, physical design, and test - helps EDA newcomers to get "up-and-running" quickly
- Includes comprehensive coverage of EDA concepts, principles, data structures, algorithms, and architectures - helps all readers improve their VLSI design competence
- Contains latest advancements not yet available in other books, including Test compression, ESL design modeling, large-scale floorplanning, placement, routing, synthesis of clock and power/ground networks - helps readers to design/develop testable chips or products
- Includes industry best-practices wherever appropriate in most chapters - helps readers avoid costly mistakes
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Inside This Book
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Key Phrases - Statistically Improbable Phrases (SIPs):
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binary search, digital integrated circuits, mask bit, ready list, clock network design, dominance fault collapsing, combinational logic minimization, skew commitment, scan extraction, compacted floorplan, scan design rules, sequential compactor, combinational compactor, jumper insertion, differential fault simulation, serial fault simulation, fault coverage goal, serial scan mode, floorplanning considerations, fault coverage loss, maximum sink delay, speedup delay model, gain bucket data structure, tilted rectangular region, adjacent scan cells Key Phrases - Capitalized Phrases (CAPs): (learn more)
Computer-Aided Design, Design Automation Conf, New York, Test Conf, Test of Computers, San Francisco, Computer Aided Design, Morgan Kaufmann, Mentor Graphics, Cadence Design Systems, Englewood Cliffs, Europe Conf, Kluwer Academic, University of California, Computer Design, San Jose, Second Edition, Int Conf, Solid-State Circuits Conf, Cambridge University Press, Int Symp, Proc Int, The Dimensions of Modules, Width Height, John Wiley Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Index | Surprise Me!
binary search, digital integrated circuits, mask bit, ready list, clock network design, dominance fault collapsing, combinational logic minimization, skew commitment, scan extraction, compacted floorplan, scan design rules, sequential compactor, combinational compactor, jumper insertion, differential fault simulation, serial fault simulation, fault coverage goal, serial scan mode, floorplanning considerations, fault coverage loss, maximum sink delay, speedup delay model, gain bucket data structure, tilted rectangular region, adjacent scan cells Key Phrases - Capitalized Phrases (CAPs): (learn more)
Computer-Aided Design, Design Automation Conf, New York, Test Conf, Test of Computers, San Francisco, Computer Aided Design, Morgan Kaufmann, Mentor Graphics, Cadence Design Systems, Englewood Cliffs, Europe Conf, Kluwer Academic, University of California, Computer Design, San Jose, Second Edition, Int Conf, Solid-State Circuits Conf, Cambridge University Press, Int Symp, Proc Int, The Dimensions of Modules, Width Height, John Wiley Browse Sample Pages:
Front Cover | Table of Contents | First Pages | Index | Surprise Me!
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