Timing Analysis and Simulation for Signal Integrity Engineers (Hardcover)

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Key Phrases: interconnect skew, signal integrity engineers, slope derating factor, Express Case Study, Chip-to-Chip Timing, Temperature Range (more...)

Editorial Reviews

Product Description

Every day, companies call upon their signal integrity engineers to make difficult decisions about design constraints and timing margins. Can I move these wires closer together? How many holes can I drill in this net? How far apart can I place these chips? Each design is unique: there’s no single recipe that answers all the questions. Today’s designs require ever greater precision, but design guides for specific digital interfaces are by nature conservative. Now, for the first time, there’s a complete guide to timing analysis and simulation that will help you manage the tradeoffs between signal integrity, performance, and cost.

 

Writing from the perspective of a practicing SI engineer and team lead, Greg Edlund of IBM presents deep knowledge and quantitative techniques for making better decisions about digital interface design. Edlund shares his insights into how and why digital interfaces fail, revealing how fundamental sources of pathological effects can combine to create fault conditions. You won’t just learn Edlund’s expert techniques for avoiding failures: you’ll learn how to develop the right approach for your own projects and environment.

 

Coverage includes

•  Systematically ensure that interfaces will operate with positive timing margin over the product’s lifetime–without incurring excess cost

•  Understand essential chip-to-chip timing concepts in the context of signal integrity

•  Collect the right information upfront, so you can analyze new designs more effectively

•  Review the circuits that store information in CMOS state machines–and how they fail

•  Learn how to time common-clock, source synchronous, and high-speed serial transfers

•  Thoroughly understand how interconnect electrical characteristics affect timing: propagation delay, impedance profile, crosstalk, resonances, and frequency-dependent loss

•  Model 3D discontinuities using electromagnetic field solvers

•  Walk through four case studies: coupled differential vias, land grid array connector, DDR2 memory data transfer, and PCI Express channel

•  Appendices present a refresher on SPICE modeling and a high-level conceptual framework for electromagnetic field behavior

Objective, realistic, and practical, this is the signal integrity resource engineers have been searching for.

 

Preface xiii

Acknowledgments xvi

About the Author xix

About the Cover xx

 

Chapter 1: Engineering Reliable Digital Interfaces 1

Chapter 2: Chip-to-Chip Timing 13

Chapter 3: Inside IO Circuits 39

Chapter 4: Modeling 3D Discontinuities 73

Chapter 5: Practical 3D Examples 101

Chapter 6: DDR2 Case Study 133

Chapter 7: PCI Express Case Study 175

 

Appendix A: A Short CMOS and SPICE Primer 209

Appendix B: A Stroll Through 3D Fields 219

 

Endnotes 233

Index 235

 

About the Author

Greg Edlund’s career in signal integrity began in 1988 at Supercomputer Systems, Inc., where he simulated and measured timing characteristics of bipolar embedded RAMs used in the computer’s vector registers. Since then, he has participated in the development and testing of nine other high-performance computing platforms for Cray Research, Inc., Digital Equipment Corp., and IBM Corp. He has had the good fortune of learning from many talented engineers while focusing his attention on modeling, simulation, and measurement of IO circuits and interconnect components. A solid physical foundation and practical engineering experience combine to form a valuable perspective on optimizing performance, reliability, and cost.

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Product Details

• Hardcover: 272 pages
• Publisher: Prentice Hall PTR; 1 edition (November 1, 2007)
• Language: English
• ISBN-10: 0132365049
• ISBN-13: 978-0132365048
• Product Dimensions: 9.4 x 7.2 x 0.8 inches
• Shipping Weight: 1.4 pounds (View shipping rates and policies)
• Average Customer Review: 3.0 out of 5 stars  See all reviews (3 customer reviews)
• Amazon.com Sales Rank: #615,779 in Books (See Bestsellers in Books)

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• This item is part of The Prentice Hall Modern Semiconductor Design Series Series.

Customer Reviews

Most Helpful Customer Reviews

3 of 4 people found the following review helpful:

1.0 out of 5 stars Worst SI book around, May 5, 2008

By	meowfast "anonymous" (USA) - See all my reviews

Normally when an author writes a book he/she wants to write about a topic where they can pass on some knowledge to their readers. I have no idea why this book was written or published. It is absent of any useful information that isn't plain common sense. There is a chapter on IBIS models, OK but I can find all that information for free on the internet. A chapter on different ways to transfer data between chips. So what? that stuff isn't something engineers need to read a book to figure out. There is chapter on using a 3D modeler. So unless you work for a company willing to spend the money and you are actually going to run the tool yourself the information in this book on 3D modeling is easily forgettable. I learned nothing new about signal integrity from this book, I learned nothing of practical value from this book. Do not waste your money on this useless book. Buy Bogatin's SI book or Howard Johnson's books. They at least have practical information.

2 of 3 people found the following review helpful:

4.0 out of 5 stars Great basic introduction, December 26, 2007

By	JM "Derek" (Germany) - See all my reviews

If you are new to the simulation world (apart from some basic SPICE in college) with words like IBIS models, 3D EM simulation being new to you then this is an excellent book to start. If you are already experienced in the simulation area and looking for an advanced book this is not it.

I give 4 stars because I would have liked that the author went more deep in some areas even for a basic simulation book.

Apart from that a great quick read even if you are experienced in this area.

1 of 2 people found the following review helpful:

4.0 out of 5 stars Excellent introduction to timing analysis/simulation for SI engineers who just joins the field , February 16, 2008

By	Nam D. Nguyen (Austin, TX) - See all my reviews (REAL NAME)

Most current SI books focus on explaining the origin and the modeling of electrical phenomena on PCBs, but barely address the practical but important question of how to systematically assess the impact of these phenomena and a host of other issues on the system timing budget. Issues such as: Read/Write timing, impedance tolerance, pin-to-pin capacitance variation, DIMM connector crosstalk, Vref AC noise and resistor tolerance, slope derating factor, etc.
This is not a from-A-to-Z cook book where you just blindly follow a set of instructions, but rather a collection of insights and experiences in dealing with these issues in the author's career that he has distilled into a systematic checklist for assessing the "heath" of the system timing in the midst of all of these budget timing corruptors. The 2 (substantial) case studies of DDR2 and PCI Express interfaces give reader solid examples of how an SI engineer may want to systematically go about doing his job.
It is also interesting to note that the author also points out that all problems that prevent SI engineers from doing a good job are not necessarily always technical in nature. How do you deal with a vendor that is reluctant to provide you with quality IBIS models ? Well, you will find a (good) solution to this problem in the book, too.
I am an electrical engineer who is in the process of making the transition from on-chip device/circuit modeling to the challenging world of off-chip signal integrity. I have found this book filled with fundamental technical knowledge about system timing that a new comer to the field of SI should know, practical advices, sound investigation strategies, and real-life examples that I can learn from and apply in my daily work.