Advanced ASIC Chip Synthesis Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime® (Hardcover)

~ (Author) "As deep sub-micron semiconductor geometries shrink, traditional methods of chip design have become increasingly difficult..." (more)
Key Phrases: clock network delay, structured netlist, inserted netlist, Design Compiler, Tue Nov, Path Type (more...)

Editorial Reviews

Product Description

Advanced ASIC Chip Synthesis: Using Synopsys TM Design CompilerTM Physical CompilerTM and PrimeTime TM, Second Edition describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted for VDSM (Very-Deep-Sub-Micron) technologies is covered in detail.

The emphasis of this book is on real-time application of Synopsys tools, used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, sub-micron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, physical synthesis, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-around described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basis of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solution. Target audiences for this book are practicing ASIC design engineers and masters level students undertaking advanced VLSI courses on ASIC chip design and DFT techniques.

Product Details

• Hardcover: 360 pages
• Publisher: Springer; 2nd edition (December 1, 2001)
• Language: English
• ISBN-10: 0792376447
• ISBN-13: 978-0792376446
• Product Dimensions: 9.3 x 6.5 x 1 inches
• Shipping Weight: 1.4 pounds (View shipping rates and policies)
• Average Customer Review: 3.5 out of 5 stars  See all reviews (2 customer reviews)
• Amazon.com Sales Rank: #1,173,841 in Books (See Bestsellers in Books)

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Customer Reviews

Most Helpful Customer Reviews

2 of 2 people found the following review helpful:

4.0 out of 5 stars hands on guide, November 12, 2005

By	V. Ananth "Nemesis" (CA, USA) - See all my reviews (REAL NAME)

This book is geared towards the synopsys synthesis tools (as evident in the title). It gives brief explanations about vhdl and verilog coding style (which can be found in many other books).
The actual useful part was that the book explored the commonly used synthesis commands in synopsys, and also had explanations on the steps to follow to succesfully synthesize rtl. These ideas can also be used on synthesis tools from other vendors.

This book is good for people already familiar with front end rtl design and are looking into moving to backend.

3 of 6 people found the following review helpful:

3.0 out of 5 stars ok for an introduction to the tools, March 20, 2003

By A Customer

This book is interesting as an introduction to these tools but needs more depth