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System-on-Chip Test Architectures: Nanometer Design for Testability (Systems on Silicon) by Laung-Terng Wang |
by Miron Abramovici
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by John L. Hennessy
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CMOS VLSI Design: A Circuits and Systems Perspective (3rd Edition) by Neil Weste |
by Mark Burns
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The book consists of:
Part I: Introduction, Test Process and ATE, Test Economics and Product Quality, Fault Modeling;
Part II: Logic and Fault Simulation, Testability Measures, Combinatorial ATPG, Sequential ATPG, Memory Test, DSP-Based Analog Test, Model-Based Analog Test, Delay Test, IDDQ Test;
Part III: DFT and Scan Design, BIST, Boundary Scan, Analog Test Bus, System Test and Core-Based Design, Future Testing;
Appendices: Cyclic Redundancy Code Theory, Primitive Polynomials, Books on Testing; Bibliography: over 700 entries.
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76% buy the item featured on this page: Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits (Frontiers in Electronic Testing Volume 17) $83.06 |
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11% buy VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon) $43.73 |
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7% buy System-on-Chip Test Architectures: Nanometer Design for Testability (Systems on Silicon) $55.96 |
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4% buy High Performance Memory Testing: Design Principles, Fault Modeling and Self-Test (Frontiers in Electronic Testing) $159.00 |
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