A Verilog HDL Primer, Third Edition (Hardcover)

~ J. Bhasker (Author)

Editorial Reviews

Review

" I would recommend as text for a course as part of Electrical Engineering curriculum" -- Lincoln A. McLoud, Bell Labs

"I have found the book easy to read, and an excellent reference" -- Sharad Seth, University of Nebraska at Lincoln

"This text is a definitive learning resource and an excellent reference for the experienced designer." -- Vincent Zeyak Jr., Agere Systems

Product Description

- Written for new users. - Explains the language through simple examples. - Explains the syntax of language using commonly-used design terminology. - Explains the behavioral style, the dataflow style, and structural style in detail. - Concepts of delay and timing are clearly explained. - Testbench writing is made easier by providing a number of examples. - Many hardware modeling examples have also been provided to make this an excellent reference.

Also includes exercises for every chapter and expanded coverage of more language features including test bench writing strategies.

Third edition is based on IEEE Verilog 2001 Standard. It includes explanations of all the new features introduced in this version of the language, with examples.

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Product Details

• Hardcover: 400 pages
• Publisher: Star Galaxy Publishing; 3rd edition (January 2005)
• ISBN-10: 0965039161
• ISBN-13: 978-0965039161
• Product Dimensions: 9.2 x 7.2 x 1 inches
• Shipping Weight: 1.6 pounds (View shipping rates and policies)
• Average Customer Review: 5.0 out of 5 stars  See all reviews (3 customer reviews)
• Amazon.com Sales Rank: #324,576 in Books (See Bestsellers in Books)

Customer Reviews

Most Helpful Customer Reviews

11 of 14 people found the following review helpful:

5.0 out of 5 stars Excellent Book on Verilog, January 2, 2008

By	Michael Andrews "Engineering is FUN (usually)!" (Lynnwood, WA) - See all my reviews (REAL NAME)

Very impressive book. Well written, the sections 'flow' nicely, thoroughly covers Verilog, and includes examples with clear explanations. Excellent index. I have about 6 years of design experience in VHDL and 18 years of embedded C development, 34 years in Engineering, so picking up Verilog went quickly.

I give a lot of credit to this book for keeping clear the big and small 'pictures' of what makes up Verilog. Highly recommend it to both new and 'seasoned' (I refuse to say 'old' :-) ) HDL designers. Great addition to your Engineering library. But unlike many books in most Engineering libraries, you'll actually use this one. :-)

5 of 6 people found the following review helpful:

5.0 out of 5 stars Great Verilog book for Beginners, April 22, 2008

By	Joseph J. Pedalino - See all my reviews (REAL NAME)

This book is well organized from beginning to end and the index is excellent for finding what you need. I found that the examples are complete and relevant to what you need to get started with Verilog. Each chapter explains the subject matter with enough examples so that the reader can understand the subject. Compiler directives are covered well enough for the beginner to use the commands. Memories were covered in sufficient detail so that I could create a RAM for my lab class. Even the $readmemh and $readmemb directives were covered. I enjoyed reading the book because it is well laid out complete. I think that the beginning student will like and enjoy using this book.

7 of 13 people found the following review helpful:

5.0 out of 5 stars Great book, July 18, 2005

By	D Cohen "Dan" (Cranford, NJ USA) - See all my reviews (REAL NAME)

Hi,

Great book.

Very good introduction to the newer releases of Verilog, includes useful code examples. Clearly explains what is synthesizable and what is not.

Dan