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A Designer's Guide to Built-in Self-Test (Frontiers in Electronic Testing)
 
 

A Designer's Guide to Built-in Self-Test (Frontiers in Electronic Testing) (Hardcover)

~ (Author) "There are three phases in the life-cycle of a product where testing is of critical importance..." (more)
Key Phrases: output response compaction, general sequential logic, loopback multiplexers, Designer's Guide, Designers Guide, Autonomous Test (more...)
4.0 out of 5 stars  See all reviews (1 customer review)

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Frequently Bought Together

Customers buy this book with Testing Static Random Access Memories: Defects, Fault Models and Test Patterns (Frontiers in Electronic Testing) by Said Hamdioui

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Product Description

A recent technological advance is the art of designing circuits to test themselves, referred to as a Built-In Self-Test (BIST). This idea was first proposed around 1980 and has grown to become one of the most important testing techniques at the current time, as well as for the future. This book is written from a designer's perspective and describes the major BIST approaches that have been proposed and implemented since 1980, along with their advantages and limitations. The BIST approaches include the Built-In Logic Block Observer, pseudo-exhaustive BIST techniques, Circular BIST, scan-based BIST, BIST for regular structures, BIST for FPGAs and CPLDs, mixed-signal BIST, and the integration of BIST with concurrent fault detection techniques for on-line testing. Particular attention is paid to system-level use of BIST in order to maximize the benefits of BIST through reduced testing time and cost as well as high diagnostic resolution. The author spent 15 years as a designer at Bell Labs where he designed over 20 production VLSI devices and 3 production circuit boards. Sixteen of the VLSI devices contained BIST of various types for regular structures and general sequential logic, including the first BIST for Random Access Memories (RAMs), the first completely self-testing integrated circuit, and the first BIST for mixed-signal systems at Bell Labs. He has spent the past 10 years in academia where his research and development continues to focus on BIST, including the first BIST for FPGAs and CPLDs along with continued work in the area of BIST for general sequential logic and mixed-signal systems. He holds 10 US patents (with 5 more pending) for various types of BIST approaches. Therefore, the author brings a unique blend of knowledge and experience to this practical guide for designers, test engineers, product engineers, system diagnosticians, and managers.

Product Details

  • Hardcover: 344 pages
  • Publisher: Springer; 1 edition (May 31, 2002)
  • Language: English
  • ISBN-10: 1402070500
  • ISBN-13: 978-1402070501
  • Product Dimensions: 9.4 x 6.4 x 0.9 inches
  • Shipping Weight: 1.5 pounds (View shipping rates and policies)
  • Average Customer Review: 4.0 out of 5 stars  See all reviews (1 customer review)
  • Amazon.com Sales Rank: #2,216,322 in Books (See Bestsellers in Books)

    Popular in this category: (What's this?)

    #41 in  Books > Professional & Technical > Engineering > Electrical & Electronics > Measurements

More About the Author

Charles E. Stroud
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Inside This Book (learn more)
First Sentence:
There are three phases in the life-cycle of a product where testing is of critical importance. Read the first page
Key Phrases - Statistically Improbable Phrases (SIPs): (learn more)
output response compaction, general sequential logic, loopback multiplexers, register adjacency, fault simulation time, bridging fault coverage, combinational logic cone, loopback data, multiple capture cycles, undefined logic value, data path circuitry, product term lines, dominant bridging fault model, normal system mode, dominant bridging faults, logic cones, analog output response, pattern sensitivity faults, single precision accumulator, path sensitization algorithm, physical layout generator, scan design techniques, test point insertion, actual fault coverage, intended system function
Key Phrases - Capitalized Phrases (CAPs): (learn more)
Designer's Guide, Designers Guide, Autonomous Test, Built-In Self Test, Count Value Holding Register, Cellular Automata, Bell Labs, Pattern Control, Shift Control, System Circuit, Magnitude Register, Cyclic Redundancy Check, Done Controller, Programmable Shift Register, Area Overhead Performance Approach Flip-Flops, Continuous Time State Variable Filter, Differential Pair, Elliptical Filter, Leapfrog Filter, Low Pass Filter, N-bit Accum Reg, Single Stage Common-Emitter Amp, Start Controller, Write Read
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What Do Customers Ultimately Buy After Viewing This Item?

VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
59% buy
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon) 5.0 out of 5 stars (1)
$43.84
A Designer's Guide to Built-in Self-Test (Frontiers in Electronic Testing)
41% buy the item featured on this page:
A Designer's Guide to Built-in Self-Test (Frontiers in Electronic Testing) 4.0 out of 5 stars (1)
$104.34

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4.0 out of 5 stars good coverage of BIST methods, February 18, 2005
By W Boudville (Terra, Sol 3) - See all my reviews
(TOP 10 REVIEWER)    (REAL NAME)      
Built-in Self-Test is now highly desirable in chip design. As the linewidth keeps decreasing, and the number of transistors rises, the sheer complexity necessitates BIST as a basic design principle. Hence Stroud offers you a recent and timely survey of BIST methods. The writing quality is not bad, and he gives a good coverage of the most common methods used in the industry.

Whether some of these prove practical in your situation is another matter, of course. If you have existing standard cells that you must use, or conform to, and a fab with specific design rules, then some BIST methods might be precluded.
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