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Test Resource Partitioning for System-on-a-Chip (FRONTIERS IN ELECTRONIC TESTING Volume 20)
 
 
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Test Resource Partitioning for System-on-a-Chip (FRONTIERS IN ELECTRONIC TESTING Volume 20) (Hardcover)

~ (Author), Vikram Iyengar (Author), Anshuman Chandra (Author) "Test resource partitioning (TRP) for a system-on-a-chip (SOC) refers to the process of partitioning monolithic test resources, such as the test data set or the..." (more)
Key Phrases: test data compression, precomputed test sets, optimum testing time, Sun Ultra, Eindhoven University of Technology, Bin Design (more...)
4.0 out of 5 stars  See all reviews (2 customer reviews)

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Product Details

  • Hardcover: 248 pages
  • Publisher: Springer; 1 edition (May 1, 2002)
  • Language: English
  • ISBN-10: 1402071191
  • ISBN-13: 978-1402071195
  • Product Dimensions: 9.6 x 6.4 x 0.8 inches
  • Shipping Weight: 1.2 pounds (View shipping rates and policies)
  • Average Customer Review: 4.0 out of 5 stars  See all reviews (2 customer reviews)
  • Amazon.com Sales Rank: #4,115,177 in Books (See Bestsellers in Books)

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    #66 in  Books > Professional & Technical > Engineering > Electrical & Electronics > Measurements

More About the Author

Krishnendu Chakrabarty
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4.0 out of 5 stars (2 customer reviews)
 
 
 
 
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1 of 1 people found the following review helpful:
3.0 out of 5 stars Good book...but not essential, February 20, 2004
By A Customer
The book is one of a kind in SoC TRP approaches and contains lot of optmization procedures mostly using ILP and MILP..but the whole point if it is just a compendium of papers by the author. Students/ researchers who have access to the digital libraries of ieee/acm/kluwer have no need to purchase the book..I had all the papers and they were interesting and the authors are like the pioneers in the field but the book and the papers are one and the same..so save your money for a different book.
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5.0 out of 5 stars Must-have book for test engineers!, April 30, 2008
By Jim Green "Jim" (Dallas, TX) - See all my reviews
This is a must-have book for test engineers or test software developers in the integrated ckts industry. The book discusses how to optimize test time, tester memory and test hardware. Treatment of complex economics issues is thoughtfully presented. The methods are not patented and can be useful to the average test engineer.
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