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1 of 1 people found the following review helpful:
5.0 out of 5 stars
Verilog with an Architectural Twist, August 15, 2008
I've been a fan or Mr. Cavanagh books beginning with his book "Digital Computer Arithmetic". Digital Computer Arithmetic: Design and Implementation (Computer Science) which I applied to an IC design I was working on (Philips 8051 derivative circa 1990). Now, I've found that I need to update my design skills and have a need to learn and apply the Verilog HDL language to apply to SDR radio design project ideas. This book fits that need. The book is not intended to be a tutorial on logic design. It is intended to be a tutorial on the complete Verilog language together with wide variety of design examples. The book begins with an overview of the Verilog language structure, language elements, and modeling concepts. Next the Verilog language elements, expressions, are covered followed by in-depth discussions of gate-level, dataflow, and behavioral, structural modeling. User-defined primitives, tasks, and functions are given apt attention. The book closes with addition design examples (a simple RISC CPU), and event queues. Note that the author uses the SILOS simulator for all examples. I found this to be an issue due to the cost of SILOS. However, a after a little research ending up with a quick trip to Wikipedia uncovered a nice low-cost Verilog design environment called LogicSim by Zeemz ([...]). Although I don't endorse any particular product, I've had no issues with LogicSim working my way thorough various portions of this book. I've also found that having a FPGA design kit (in my case a Xilinx Spartin-3 kit) is quite useful to apply the concepts. Your mileage may vary.
Note that if you are new to Verilog (but not to programming in general) the book is quite easy to read. Note that in order to fully grasp Verilog, in my opinion, you need to read the entire text (all 770+ pages) and work the examples. The explanation of Verilog is not condensed with follow-on project. The approach is to get you started with simple examples of what is presented in latter chapters. The various parts of Verilog are then covered in more depth. Some may not like this approach opting, instead, for a book that has complete projects on a specific kit (Xilinx Spartan 3, etc.). This is not the book for those individuals. There are plenty of books on Verilog. This book happens to fit my need to cover Verilog with, what I would describe, and "architectural twist". Mr. Cavanagh's other book complements this book.
The contents of the book are as follows:
Chapter 1 Introduction
Chapter 2 Overview
Chapter 3 Language Elements
Chapter 4 Expressions
Chapter 5 Gate-Level Modeling
Chapter 6 User-Defined Primitives
Chapter 7 Dataflow Modeling
Chapter 8 Behavioral Modeling
Chapter 9 Structural Modeling
Chapter 10 Tasks and Functions
Chapter 11 Additional Design Examples
Appendix A Event Queue
Appendix B Verilog Project Procedure
Appendix C Answers to Select Problems
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1 of 1 people found the following review helpful:
5.0 out of 5 stars
Another great one by Mr. Cavanagh, June 19, 2008
Clearly one of the best books written on Verilog HDL. It covers the complete Verilog language in detail, including language elements and expressions. Chapters include comprehensive coverage of built-in primitives, user-defined primitives, dataflow modeling, behavioral modeling, and structural modeling, all with numerous examples that illustrate the design principles of each modeling method. There are excellent examples on the Hamming code, the Booth algorithm, and a pipelined RISC processor, all completely designed using Verilog.
The Verilog simulator used in the book is the SILOS simulation environment from Silvaco Intenational. Design examples in the book include the design module, the test bench module, the outputs, and the waveforms. The design topics also include the associated theory.
No book will tell you how to design your particular Verilog project; however, using the principles and practices outlined in this book and your own innate ability you can accomplish anything. An excellent book for both academia and industry.
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1.0 out of 5 stars
This book is useless as a reference or tutorial, June 1, 2009
I don't know what the intended audience of this book it. But it certainly is not for people interesting in dabbling in verilog, with the intent of programming, for instance, FPGAs.
Many verilog keywords are simply missing from the index (for instance, the highly useful "signed" keyword, if you want to do signed arithmetic, had to find that out on my own). Those are are covered are given a short and pedantic description, but most are not fleshed out in any examples or explained in a complete enough way to allow you to use them after reading the "explanation".
Example, the definition of the "tri" keyword, and I quote:
The tri keyword specifies a net with multiple drivers. It has the same function as wire, but describes a three-state net.
This definition is repeated more or less verbatim again on a later page. But never again is tri mentioned, or given in any examples, at least as far as I could find in the books index.
I've had similar frustrations every time I've turned to this book for help. Useless.
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