CMOS/BICMOS ULSI presents state-of-the-art BiCMOS low-voltage, low-power design techniques for ULSI and giga-scale integration engineering, covering process integration, device modeling, and characterization. Discover the latest MOS and bipolar models; breakthroughs in copper metallization, isolation, and deep submicron processes; and new approaches to designing logic gates, latches, and flip-flops.
About the Author
KIAT-SENG YEO joined the School of Electrical and Electronic Engineering (EEE), Nanyang Technological University (NTU), Singapore in 1993. He is now the Sub-Dean of EEE, Principal Investigator of NTU's Integrated Circuit Technology Research Group, Program Manager of the System-on-Chip Flagship Project, Coordinator of the Integrated Circuit Design Research Group, Technical Chairman of the 8th and 9th International Symposium on Integrated Circuits, Devices and Systems, and a Technical Consultant. He holds six patents and published more than 100 articles in BiCMOS/CMOS integrated circuit design and technology.
SAMIR S. ROFAIL has been a teacher, researcher, and consultant in semiconductor and IC design for 20 years. From 1992 to 1999, he coordinated NTU's IC-Design group, leading intensive research on low-voltage, low-power BiCMOS/CMOS circuits. He is now a technical consultant in Waterloo, Canada.
WANG-LING GOH joined NTU in 1996. Her research interests are in the areas of silicon processing technologies, particularly the SOI structures, CMP and Copper. She holds one patent and has published over 30 articles in the above named areas.
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