"Design Automation Conf"

Key Phrases: Test Conf, Digest of Papers, Computer-Aided Design, Design Automation Conf, Test of Computers, Annual Intn'l, crosspoint faults, critical cubes, arbitrary delay model, critical path tracing, iterative array model, pseudoexhaustive testing (see more)

Key Phrases: Test Conf, Digest of Papers, Computer-Aided Design, Design Automation Conf, Test of Computers, Annual Intn'l, Computer Design, Technical Report, Journal of Research, New York, Stanford University, Bell System Technical Journal, Deduction Algorithm, Journal of Design Automation, Proc Intn'l, Combinational Networks, Computer Science Press, Some Advanced, Combinational Logic Networks, Electronic Computers, Design Automation Corrf, Intn'l Conf, New Approach, Academic Press, Decisions Implications, crosspoint faults, critical cubes, arbitrary delay model, critical path tracing, iterative array model, pseudoexhaustive testing, combinational equivalent, noncode inputs, fanout count, deductive simulation, fanout list, fanout branches, checkpoint faults, stem fault, masking probability, noncode word, universal test set, fault collapsing, percent fault coverage, unidirectional errors, one fanout, shrinkage fault, equality checker, reconvergent fanout, complete test set (see less)

Key Phrases: Test Conf, Test Symp, Test Comput, Design Automation Conf, New York, Europe Conf, linear decompressor, deductive fault simulation, scan design rules, fault coverage goal, available spare rows, failing syndrome (see more)

Key Phrases: Test Conf, Test Symp, Test Comput, Design Automation Conf, New York, Europe Conf, Computer Design, Fault-Tolerant Computing, John Wiley, Kluwer Academic, Repeat Problem, Mentor Graphics, Prentice Hall, Shift Window Capture Window Shift Window, Agilent Technologies, Solid-State Circuits, Custom Integrated Circuits Conf, Intentionally Left Blank, Palo Alto, Semiconductor Industry Association, Texas Instruments, Cambridge University Press, Circuits Syst, Digest of Papers, San Jose, linear decompressor, deductive fault simulation, scan design rules, fault coverage goal, available spare rows, failing syndrome, sequential fault simulation, untestable faults, bridging fault diagnosis, fault descriptors, nanometer age, transition count testing, memory access commands, scan extraction, adjacent scan cells, analog test buses, extended backward implications, redundancy analysis algorithms, scan input pin, test data volume, failing chip, space compactor, compressed stimulus, small delay defects, statistical fault analysis (see less)

Key Phrases: Low-Power Electronics Design, Solid-State Circuits, New York, Design Automation Conf, San Francisco, Kluwer Academic Publishers, antiparallel current sources, nonbinary divider, precharged latch, hardware intensity, system description input, fixed mapping organization (see more)

Key Phrases: Low-Power Electronics Design, Solid-State Circuits, New York, Design Automation Conf, San Francisco, Kluwer Academic Publishers, Advanced Res, Texas Instruments, John Wiley, San Diego, Computer Science, San Jose, Devices Meeting, Addison-Wesley Reading, Europe Conf, Santa Clara, University of California-Berkeley, Blast Rail, Cambridge University Press, Prentice Hall, Reference Manual, Computer Design, Device Lett, Huntington Beach, Specman Elite, antiparallel current sources, nonbinary divider, precharged latch, hardware intensity, system description input, fixed mapping organization, precharged node signal, smart battery systems, weak inversion logic, fuel cell core, drowsy mode, parallelized shift register, voltage drop analysis, architecture analyzer, nanometric technologies, new technology node, battery cost routing, new channel materials, operand isolation, software power analysis, code expander, miniature fuel cells, reverse body bias, execution bypass, statistical timing analysis (see less)

Key Phrases: Design Automation Conf, New York, Computer Aided Design, Computer-Aided Design, Electronic Packaging, John Wiley, degenerated clique, permitted connectivity, interconnect connectivity, same node configuration, clause chords, unplaced module (see more)

Key Phrases: Design Automation Conf, New York, Computer Aided Design, Computer-Aided Design, Electronic Packaging, John Wiley, Journal of Applied Math, New Approach, College Park, Englewood Cliffs, Pdi Pdi, degenerated clique, permitted connectivity, interconnect connectivity, same node configuration, clause chords, unplaced module, gridded workspace, demanded connectivity, routable area, vertical grid edge, compound cliques, routing length, detour length, sorted edge list, problem with rectilinear distance, odd cycle cover, total hazard rate, total device area, crossing graph, ith device, signal interconnections, redundant length, node minimum spanning tree, scanned grids, reliability placement (see less)