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Embedded SoPC Design with Nios II Processor and Verilog Examples 1st Edition

5.0 out of 5 stars 3 customer reviews
ISBN-13: 978-1118011034
ISBN-10: 1118011031
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Editorial Reviews

About the Author

Dr. Pong P. Chu is Associate Professor in the Department of Electrical and Computer Engineering at Cleveland State University in Ohio. He has taught undergraduate- and graduate-level digital systems and computer architecture courses for more than a decade and has received instructional grants from the National Science Foundation and Cleveland State University.

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Product Details

  • Hardcover: 782 pages
  • Publisher: Wiley; 1 edition (April 30, 2012)
  • Language: English
  • ISBN-10: 1118011031
  • ISBN-13: 978-1118011034
  • Product Dimensions: 7.4 x 2 x 10.2 inches
  • Shipping Weight: 3.3 pounds (View shipping rates and policies)
  • Average Customer Review: 5.0 out of 5 stars  See all reviews (3 customer reviews)
  • Amazon Best Sellers Rank: #1,104,806 in Books (See Top 100 in Books)

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Top Customer Reviews

Format: Hardcover Verified Purchase
Dr. Pong Chu has done Yoeman's work here. Unlike most applied engineering texts in which the author does a lot of hand-waving; iterating already well published knowledge, and inserting a desultory set of white papers and application notes, Professor Chu has done some serious heavy lifting in this book. Dr. Chu has basically produced the same book over a number of years using two flavors VHDL and Verilog on two FPGA platforms, Xilinx and Altera. However I say that in a good way, as this book is very clear, free of all but minor errors, and incredibly detailed with practical examples. The charts and graphs alone are a masterpieces and I'm sure they exist no where else. The amount of work Chu must have spent putting this all together in a presentable way is incredible. You could read the 1,000+ page SOPC/Qsys spec Altera generously provides but it will only serve as confusing soporific which will usually prove unhelpful unless you are after a very specific question and have the time to wade through it.

There is both practical and recondite knowledge in this tome, which will take the graduate student, or practicing engineer, on the path to success as more company's move away from the outdated 8-bit assembly programed MCU's, more suitable for toasters and dishwashers, and into the exciting world of system on a chip (SoC). This book is focused on developing an up-loadable hardware architecture produced from HDL, and the SOPC(now Qsys) GUI for the FPGA, and then using the fungible Eclipse IDE to write C code to instruct it on how to behave. The Altera and Xilinx versions both utilize their respective free tool chains. No there probably wont be a Microsemi or Lattice version, but really who cares as you got the two big boys covered (Xilinx and Altera).
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Format: Hardcover
FPGA SoC (system on a Chip) and hardware-software co-design are emerging and exciting technologies. Developing such system is quite complex, requiring knowledge from software algorithm to hardware design and everything in between. This book tries to tackle the problem and covers a wide range of topics, including hardware design via Verilog HDL (Hardware Description Language), FPGA based soft-core processor, custom I/O peripherals, hardware accelerators, bus interface, device drivers, embedded programming, and the integration of customer hardware, processor, and software.

The book is divided into 4 parts:
- Part I introduces key Verilog language constructs and digital design concepts, and systematically shows how to implement combinational circuit, sequential circuit, FSM, and FSMD (FSM with data path).
- Part II is basically a stand-alone introduction to embedded C programming within Altera Nios II processor framework. It shows how to create a Nios based system with predesigned I/O cores, develop software with Altera IDE, and construct device drivers to access IO cores.
- Part III provides an in-depth overview of Nios II bus structure and discusses the development of custom IO peripherals (i.e., IP cores). It utilizes the hardware techniques of Part I and software driver techniques of Part II to design a series of moderately complex IP cores, including a PS2 keyboard/mouse controller, a video controller with SRAM frame buffer, an audio codec controller, and an SD card controller with FAT file system.
-Part IV demonstrates how to convert a software algorithm into a hardware accelerator. Three case studies are provided: GCD, Mandelbrot set, and DDFS. Their software and hardware implementations and performance are compared.
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Format: Hardcover Verified Purchase
It's hard to believe this book only has two reviews. I bought it 2 years ago and read it cover to cover while performing all of the examples on my Altera DE1 board. This book is much better than any physical or online course out there. Examples are clear and easy to interpret. I only wish my instructors in college used books like this.

I wrote an SRAM controller using the examples. I modified it slightly and you can view it on Youtube. I don't want to post any links here but you can do a search for SRAM CONTROLLER. Hope this review helps.
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