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Hdl Chip Design: A Practical Guide for Designing, Synthesizing & Simulating Asics & Fpgas Using Vhdl or Verilog Reprint Edition
- ISBN-100965193438
- ISBN-13978-0965193436
- EditionReprint
- PublisherDoone Pubns
- Publication dateMarch 1, 1998
- LanguageEnglish
- Dimensions21.85 x 28.7 x 11.42 inches
- Print length448 pages
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Product details
- Publisher : Doone Pubns; Reprint edition (March 1, 1998)
- Language : English
- Hardcover : 448 pages
- ISBN-10 : 0965193438
- ISBN-13 : 978-0965193436
- Item Weight : 9.1 ounces
- Dimensions : 21.85 x 28.7 x 11.42 inches
- Best Sellers Rank: #1,286,740 in Books (See Top 100 in Books)
- #4,888 in Technology (Books)
- #26,737 in Engineering (Books)
- #88,409 in Textbooks (Books)
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This book walks you through things for both VHDL and Verilog, but directly addresses what is and is not synthesizable and what is a grey area. For many of the code snippets, it goes so far as to show you the result of synthesis at the gate level (wires, AND/OR's, NAND/NOR's, XOR's, XNOR's, etc.) - so you can check your understanding of things at as low a level as you'd like.
This, coupled with advice on how to avoid the toolchain inferring latches, when to assign initial/default values, etc., has really helped me clear away some fog on this subject.
My one issue with the book is its simultaneous treatment of VHDL and Verilog. The book is a little more cumbersome than it would otherwise be (at least on a first read) by having these interleaved. On a second reading, or if I knew more, the interleaving would probably be beneficial.
Overall, this is a good book to have if you need to switch between Verilog and VHDL and need to compare and grab fundamental concepts.
Despite of the claim that "Its accuracy has been verified through machine-processing of all the examples, and by leading industry experts." the book contains a number of errors in the example code.
The book binding is not good; the book falls a part easily. Mine has to go in a binder now.
It covers and compares VHDL and Verilog impartially, describing their differences, strengths and weaknesses.
It has side by side VHDL and Verilog code - if you know one language, this is an excellent reference to the other language. My copy of the book was used by several engineers to cross train themselves in Verilog or VHDL.
Code is given for practical, real world circuits. From multiplexers to FSM to ALU, it is all in there. Each "class" of circuit is given its own chapter and covered in depth. The FSM chapter is 74 pages, for example.
There are many illustrations of the resulting synthesized logic. A picture is worth a thousand words, and seeing the result of different coding styles is very instructive. For example, coded one way, you get asynchronous resets, coded another, you get synchronous set/reset on your flipflops.
Beyond just a cookbook of VHDL and Verilog reference code, the book does cover such topics as scan test structures, simulation, hierarchial design, but these topics do not receive an in-depth coveraqe. There is an entire chapter dedicated to writing test harnesses, again with side-by-side code for VHDL and Verilog.
My copy saw use in multiple real world projects, by multiple, experienced engineers. It was most often used by VHDL (or Verilog) experts to learn Verilog (or VHDL). It was also used as a reference for coding particular structures. Quickly providing the answer to questions like "how do I code a carry lookahead in Verilog?" Eventually, I had to stop loaning it out as the pages began to fall out from the high volume of use. Unfortunately, it is no longer in print, so I have to use it very carefully, and coworkers are forced to struggle with inferior texts for reference.
The most important thing about this book is the way it shows you how the synthesis tool interprets your code, which is the single most important aspect of VHDL/Verilog coding. It saves you the frustration of finding out by trial and error, and shows you ways of avoiding nasty synthesis problems.
This book is a must for any serious designer's library, and great for starters as well.







