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Introduction to Verilog Paperback – November 1, 2000
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About the Author
Bob Zeidman is the founder and president of Zeidman Consulting. Since 1987, Bob has designed ASICs, FPGAs, and PC boards for RISC-based parallel processor systems, laser printers, network switches and routers, and other real time systems. His clients have included Apple Computer, Cisco Systems, Ricoh Systems, and Texas Instruments. He has written technical papers on hardware and software design methods, and has taught courses on Verilog, ASIC, and FPGA design at engineering conferences throughout the world. Bob is certified in the use of CodeSuite®. He holds a master's degree from Stanford University and two bachelor's degrees from Cornell University and holds several patents. He is the author of The Software IP Detective's Handbook, Verilog Designer's Library, Introduction to Verilog, and Designing with FPGAs and CPLDs. Bob is a Senior Member of the IEEE and was the recipient of the 1994 Wyle/EE Times American by Design Award and the 2003 Jolt Reader's Choice Award in addition to other engineering and scholastic awards. Bob has also won awards for writing and for the production and direction of short films. Bob was also the president, CEO, and founder of The Chalkboard Network, an e-learning company for engineers and business professionals and is currently the president of Zeidman Technologies, a company developing unique software tools for efficient development of embedded systems.
Excerpt. © Reprinted by permission. All rights reserved.
This self-study guide came about as the result of the popularity of my textbook, Verilog Designers Guide. That book is an intermediate to advanced level reference book about the Verilog Hardware Description Language. The book has a lot of good advice and a large number of well-documented Verilog routines that can be used to create real-world hardware. Shortly after its publication, the Institute of Electrical and Electronics Engineers (IEEE) approached me to create a study guide based on the book. I realized that for those who already knew Verilog, the book was fairly self-explanatory. However, it could be difficult to navigate for those who are just learning. Yet the functions in the book make ideal examples and problems for learning the language. With that in mind I decided to create this introductory study guide using my textbook for illustration and problem assignments. This study guide is based on the Verilog seminar that I give around the world. Over the years ! Ive used the feedback from students to try to make this the best introductory Verilog course available. I hope Ive succeeded. If you want to comment, either to congratulate me on the excellent job Ive done, to ask a question, to point out a mistake or misconception, or to suggest improvements for the future, or simply to complain, please do so. I welcome all feedback.
Hardware Description Languages (HDLs) use statements, like programming language statements, in order to define, simulate, synthesize, and layout hardware. One of the main HDLs is Verilog, a widely used and standardized language. Verilog can be used to design anything from the most complex ASIC to the least complex PAL. As ASICs and FPGAs become more complex, HDLs become a necessity for their design.
This course teaches how to use Verilog to design and simulate hardware. It begins by explaining the benefits of HDLs over other design entry methods, including its ability to model different levels of abstraction, its reusability, and documentability. Next, the syntax of the Verilog language is explained in detail. By the end of the course, the student should be able to design and simulate real hardware using Verilog.
The book is aimed at electrical engineering students and practicing electrical engineers who are not yet familiar with Verilog. It is intended for engineers who wish to cover a lot of ground toward understanding and using Verilog to create real designs. The prerequisite is a good knowledge of digital logic design. Knowledge of programming languages, such as C or C++, and knowledge of other Hardware Description Languages (HDLs) such as VHDL, is beneficial but not mandatory. --This text refers to an out of print or unavailable edition of this title.
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Top customer reviews
If you are looking for a quick way to learn how to design digital systems using Verilog, then this book is a great place to start. And unlike some reviewers, I've never met the author and have nothing to gain or lose by my reviews, which is why I use my real name. Search for me on LinkedIn under kenarnoldentrepreneur if you have any doubts that this is a genuine review and I'm who I say I am.
Im trying to teach myself Verilog on the daily subway commute.
So far its informative, well laid out, and just a touch of humour to keep it going.
The problem is the code listings are very poorly formatted in the kindle edition.
I suspect its a factor of not having enough columns, which results in each original line spanning two or three lines in the kindle.
Ive tried reducing the font and switching to landscape mode with limited results.
As it is, it becomes impossible to follow the code listings or sample questions.
I strongly request the author work on a kindle friendly edition.
Not the kind of book to have by your side when actually designing and debugging code.